VerilogDataBase.h

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#ifndef VERILOGPARSER_DATABASE_H
#define VERILOGPARSER_DATABASE_H
 
#include <string>
#include <vector>
#include <iostream>
#include <fstream>
#include <sstream>
#include <cassert>
#include <limits>

namespace VerilogParser {

enum PinType
{
    kINPUT = 0x1, 
    kOUTPUT = 0x2,
    kREG = 0x4
};

struct Range 
{
    int low; 
    int high; 
    Range() {low = high = std::numeric_limits<int>::min();}
    Range(int l, int h) : low(l), high(h) {}
};

struct GeneralName
{
    std::string name; 
    Range range; 

    GeneralName(std::string const& n = "") {name = n; range.low = range.high = std::numeric_limits<int>::min();}
    GeneralName(std::string const& n, int low, int high) {name = n; range.low = low; range.high = high;}
};

struct NetPin
{
    std::string net; 
    std::string pin; 
    Range range; 

    union Extension {
        int constant; 
        std::vector<GeneralName>* vNetName; 
    } extension; 

    NetPin(std::string& n, std::string& p, Range const& r = Range())
    {
        net.swap(n);
        pin.swap(p);
        range = r;
    }

    NetPin(std::string& n, std::string& p, Range const& r, int c)
    {
        net.swap(n);
        pin.swap(p);
        range = r;
        extension.constant = c; 
    }

    NetPin(std::string& n, std::string& p, std::vector<GeneralName>& vNetName)
    {
        net.swap(n);
        pin.swap(p);
        range = Range();
        extension.vNetName = new std::vector<GeneralName>();
        extension.vNetName->swap(vNetName); 
    }

    NetPin(NetPin const& rhs)
    {
        copy(rhs);
    }

    NetPin& operator=(NetPin const& rhs)
    {
        if (this != &rhs)
            copy(rhs);
        return *this;
    }

    ~NetPin()
    {
        if (net == "VerilogParser::GROUP_NETS")
        {
            delete extension.vNetName; 
        }
    }

    void copy(NetPin const& rhs)
    {
        if (net == "VerilogParser::GROUP_NETS")
        {
            delete extension.vNetName; 
        }
        net = rhs.net; 
        pin = rhs.pin; 
        range = rhs.range; 
        if (net == "VerilogParser::CONSTANT_NET")
        {
            extension.constant = rhs.extension.constant; 
        }
        else if (net == "VerilogParser::GROUP_NETS")
        {
            extension.vNetName = new std::vector<GeneralName> (*rhs.extension.vNetName);
        }
    }
};

class StringArray : public std::vector<std::string>
{
    public: 
        typedef std::vector<std::string> base_type;
        using base_type::size_type;
        using base_type::value_type;
        using base_type::allocator_type;

        StringArray(const allocator_type& alloc = allocator_type())
            : base_type(alloc) {}

        StringArray(size_type n, const value_type& val, const allocator_type& alloc = allocator_type())
            : base_type(n, val, alloc) {}
};

class GeneralNameArray : public std::vector<GeneralName>
{
    public: 
        typedef std::vector<GeneralName> base_type;
        using base_type::size_type;
        using base_type::value_type;
        using base_type::allocator_type;

        GeneralNameArray(const allocator_type& alloc = allocator_type())
            : base_type(alloc) {}

        GeneralNameArray(size_type n, const value_type& val, const allocator_type& alloc = allocator_type())
            : base_type(n, val, alloc) {}
};
 
// forward declaration
class VerilogDataBase
{
    public:
        virtual void verilog_module_declaration_cbk(std::string const& module_name, std::vector<GeneralName> const& vPinName); 
        virtual void verilog_instance_cbk(std::string const& macro_name, std::string const& inst_name, std::vector<NetPin> const& vNetPin) = 0;
        virtual void verilog_net_declare_cbk(std::string const& net_name, Range const& range) = 0;
        virtual void verilog_pin_declare_cbk(std::string const& pin_name, unsigned type, Range const& range) = 0;
        virtual void verilog_assignment_cbk(std::string const& target_name, Range const& target_range, std::string const& source_name, Range const& source_range); 
 
    protected:
        void verilog_user_cbk_reminder(const char* str) const; 
};
 
} // namespace VerilogParser
 
#endif