The Xilinx mpegtsmux IP reads the elementary streams from memory and
writes the MPEG2 TS(transport stream) to memory.

The mpeg2 ts muxer follows the dma descriptor based approach. Each DMA
descriptor contains information about each of the elementary stream
buffer properties and buffer address. It reads the descriptors one after
the other and generates the TS packets with the information in the
descriptor. The IP writes the generated TS packets at the output buffer
address.

Required properties:

- compatible: must be "xlnx,tsmux-1.0"
- interrupts: interrupt number
- interrupts-parent: phandle for interrupt controller
- reg: base address and size of the IP core
- clock-names: must contain "ap_clk"
- clocks: phandle to AXI Lite

Example:
	ts2mux: ts2mux@0xa0200000 {
		compatible = "xlnx,tsmux-1.0";
		interrupt-parent = <&gic>;
		interrupts = <0 90 4>;
		reg = <0x0 0xa0200000 0x0 0x30000>;
		clock-names = "ap_clk";
		clocks = <&misc_clk_0>;
	};
