Device-Tree bindings for Xilinx SPDIF PL IP

The IP supports SPDIF based playback and capture audio

Required properties:
 - compatible: "xlnx,spdif-2.0"
 - clock-names: List of input clocks.
   Required elements for SPDIF Tx: "aud_clk_i", "s_axi_aclk", "s_axis_aclk".
   Required elements for SPDIF Rx: "aud_clk_i", "s_axi_aclk", "m_axis_aclk".
 - clocks: Input clock specifier. Refer to common clock bindings.
 - reg: Base address and address length of the IP core instance.
 - interrupts-parent: Phandle for interrupt controller.
 - interrupts: List of Interrupt numbers.
 - xlnx,spdif-mode: 0 :- receiver mode ; 1 :- transmitter mode
 - xlnx,snd-pcm: phandle to audio formatter node

Example - SPDIF Rx:
	spdif_0: spdif@80010000 {
		clock-names = "aud_clk_i", "s_axi_aclk", "m_axis_aclk";
		clocks = <&si570_1>, <&clk 71>, <&clk 71>;
		compatible = "xlnx,spdif-2.0";
		interrupt-parent = <&gic>;
		interrupts = <0 91 4>;
		reg = <0x0 0x80010000 0x0 0x10000>;
		xlnx,spdif-mode = <1>;
		xlnx,snd-pcm = <&audio_formatter_0>;
	};
