* Xilinx XDMA PL PCIe Root Port Bridge DT description

Required properties:
- #address-cells: Address representation for root ports, set to <3>
- #size-cells: Size representation for root ports, set to <2>
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.
- compatible: Should contain "xlnx,xdma-host-3.00"
- reg: Should contain XDMA PCIe registers location and length
- device_type: must be "pci"
- interrupts: Should contain AXI PCIe interrupt
- interrupt-map-mask,
  interrupt-map: standard PCI properties to define the mapping of the
	PCI interface to interrupt numbers.
- ranges: ranges for the PCI memory regions (I/O space region is not
	supported by hardware)
	Please refer to the standard PCI bus binding document for a more
	detailed explanation

For MSI DECODE mode:
- interrupt-names: Must include the following entries:
	"misc": interrupt asserted when legacy or error interrupt is received
	"msi1, msi0": interrupt asserted when an MSI is received

Interrupt controller child node
+++++++++++++++++++++++++++++++
Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #address-cells: specifies the number of cells needed to encode an
	address. The value must be 0.
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.

NOTE:
The core provides a single interrupt for both INTx/MSI messages. So,
created a interrupt controller node to support 'interrupt-map' DT
functionality.  The driver will create an IRQ domain for this map, decode
the four INTx interrupts in ISR and route them to this domain.


Example:
++++++++
MSI FIFO mode:
	xdma_0: axi-pcie@a0000000 {
		#address-cells = <3>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		compatible = "xlnx,xdma-host-3.00";
		device_type = "pci";
		interrupt-map = <0 0 0 1 &pcie_intc_0 1>,
				<0 0 0 2 &pcie_intc_0 2>,
				<0 0 0 3 &pcie_intc_0 3>,
				<0 0 0 4 &pcie_intc_0 4>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-parent = <&gic>;
		interrupts = <0 89 4>;
		ranges = <0x02000000 0x00000000 0xB0000000 0x0 0xB0000000 0x00000000 0x01000000>,
			<0x43000000 0x00000005 0x00000000 0x00000005 0x00000000 0x00000000 0x01000000>;
		reg = <0x0 0xA0000000 0x0 0x10000000>;
		pcie_intc_0: interrupt-controller {
			#address-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller ;
		};
	};

MSI DECODE mode:
	xdma_0: axi-pcie@a0000000 {
		#address-cells = <3>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		compatible = "xlnx,xdma-host-3.00";
		device_type = "pci";
		interrupt-map = <0 0 0 1 &pcie_intc_0 1>, <0 0 0 2 &pcie_intc_0 2>, <0 0 0 3 &pcie_intc_0 3>, <0 0 0 4 &pcie_intc_0 4>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-parent = <&gic>;
		interrupt-names = "misc", "msi0", "msi1";
		interrupts = <0 89 4>, <0 90 4>, <0 91 4>;
		ranges = <0x02000000 0x00000000 0xB0000000 0x0 0xB0000000 0x00000000 0x01000000>,
			<0x43000000 0x00000005 0x00000000 0x00000005 0x00000000 0x00000000 0x01000000>;
		reg = <0x0 0xA0000000 0x0 0x10000000>;
		pcie_intc_0: interrupt-controller {
			#address-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller ;
		};
	};

Versal PL PCIe host Bridge DT description.

The properties and their meanings are identical to those described in
above Xilinx XDMA PL PCIe Root Port Bridge description.
The IP supports only MSI DECODE mode.

Properties that differ are:
- compatible: Should contain "xlnx,pcie-dma-versal-2.0"

Example:
	pcie_dma_versal_0: axi-pcie@80000000 {
		#address-cells = <3>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		compatible = "xlnx,pcie-dma-versal-2.0";
		device_type = "pci";
		interrupt-map = <0 0 0 1 &psv_pcie_intc_0 1>,
				<0 0 0 2 &psv_pcie_intc_0 2>,
				<0 0 0 3 &psv_pcie_intc_0 3>,
				<0 0 0 4 &psv_pcie_intc_0 4>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-names = "misc", "msi0", "msi1";
		interrupt-parent = <&gic>;
		interrupts = <0 84 4 0 85 4 0 86 4>;
		ranges = <0x02000000 0x00000000 0xB0000000 0x0 0xB0000000 0x00000000 0x10000000>,
			 <0x43000000 0x00000005 0x00000000 0x00000005 0x00000000 0x00000000 0x01000000>;
		reg = <0x0 0x80000000 0x0 0x10000000>;
		psv_pcie_intc_0: interrupt-controller {
			#address-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller ;
		};
	};
