XILINX AXI ETHERNET Device Tree Bindings
--------------------------------------------------------

This driver supports following MAC configurations-
a) AXI 1G/2.5G Ethernet Subsystem.
b) 10G/25G High Speed Ethernet Subsystem.
c) 10 Gigabit Ethernet Subsystem.
d) USXGMII Ethernet Subsystem.
e) MRMAC Ethernet Subsystem.
f) 1G/10G/25G Switching Ethernet Subsystem.

AXI 1G/2.5G Ethernet Subsystem- also called  AXI 1G/2.5G Ethernet Subsystem,
the xilinx axi ethernet IP core provides connectivity to an external ethernet
PHY supporting different interfaces: MII, GMII, RGMII, SGMII, 1000BaseX.
It also includes two segments of memory for buffering TX and RX, as well as
the capability of offloading TX/RX checksum calculation off the processor.

Management configuration is done through the AXI interface, while payload is
sent and received through means of an AXI DMA controller. This driver
includes the DMA driver code, so this driver is incompatible with AXI DMA
driver.

MRMAC is a hardened Ethernet IP on Versal supporting multiple rates from
10G to 100G which can be used with a soft DMA controller.

The Xilinx 1G/10G/25G Switching Ethernet Subsystem contains integrated MAC
and PCS and it supports runtime switchable speeds among 1G,10G & 25G.

For details about MDIO please refer phy.txt [1].

Required properties:
- compatible	: Must be one of "xlnx,axi-ethernet-1.00.a" or
		  "xlnx,axi-ethernet-1.01.a" or "xlnx,axi-ethernet-2.01.a"
		  for 1G MAC,
		  "xlnx,ten-gig-eth-mac" for 10 Gigabit Ethernet Subsystem,
		  "xlnx,xxv-ethernet-1.0" for 10G/25G MAC,
		  "xlnx,axi-2_5-gig-ethernet-1.0" for 2.5G MAC,
		  "xlnx,xxv-usxgmii-ethernet-1.0" for USXGMII and
		  "xlnx,mrmac-ethernet-1.0" for MRMAC and
		  "xlnx,ethernet-1-10-25g-2.7" for switchable 1/10/25G IP.
- reg		: Address and length of the IO space, as well as the address
                  and length of the AXI DMA controller IO space, unless
                  axistream-connected is specified, in which case the reg
                  attribute of the node referenced by it is used.
- interrupts	: Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
		  and optionally Ethernet core.
- phy-handle	: Should point to the external phy device if exists. Pointing
		  this to the PCS/PMA PHY is deprecated and should be avoided.
		  See ethernet.txt file in the same directory.
- xlnx,rxmem	: Set to allocated memory buffer for Rx/Tx in the hardware

Required properties when configured as MRMAC:
- xlnx,mrmac-rate	: Can be 10000 or 25000 providing rate in Mbps.
- xlnx,gtlane		: Indicate the GT reset and speed control lane for the
			  the current MRMAC lane. Valid range is 0 to 3.
- xlnx,gtpll		: Handle to AXI GPIO instance for GT PLL mask control.
			  This is required to control the common PLL mask bits.
- xlnx,gtctrl		: Handle to AXI GPIO instance for GT speed and reset
			  control for each MRMAC lane.

Optional properties:
- phy-mode	: See ethernet.txt
- xlnx,phy-type	: Deprecated, do not use, but still accepted in preference
		  to phy-mode.
- xlnx,txcsum	: 0 or empty for disabling TX checksum offload,
		  1 to enable partial TX checksum offload,
		  2 to enable full TX checksum offload
- xlnx,rxcsum	: Same values as xlnx,txcsum but for RX checksum offload
- xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
		  support both 1000BaseX and SGMII modes. If set, the phy-mode
		  should be set to match the mode selected on core reset (i.e.
		  by the basex_or_sgmii core input line).
- clock-names: 	  Tuple listing input clock names. Possible clocks:
		  s_axi_lite_clk: Clock for AXI register slave interface
		  axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
		  ref_clk: Ethernet reference clock, used by signal delay
			   primitives and transceivers
		  mgt_clk: MGT reference clock (used by optional internal
			   PCS/PMA PHY)

		  Note that if s_axi_lite_clk is not specified by name, the
		  first clock of any name is used for this. If that is also not
		  specified, the clock rate is auto-detected from the CPU clock
		  (but only on platforms where this is possible). New device
		  trees should specify all applicable clocks by name - the
		  fallbacks to an unnamed clock or to CPU clock are only for
		  backward compatibility.
- clocks: 	  Phandles to input clocks matching clock-names. Refer to common
		  clock bindings.
 - mdio		: Child node for MDIO bus. Must be defined if PHY access is
		  required through the core's MDIO interface (i.e. always,
		  unless the PHY is accessed through a different bus).
- dma-coherent		: Present if dma operations are coherent.
- xlnx,eth-hasnobuf	: Used when 1G MAC is configured in non-processor mode.
- xlnx,rxtsfifo		: Configures the axi fifo for receive timestamping.

Optional properties for connected DMA node:
- xlnx,addrwidth	: Specify the width of the DMA address space in bits.
			  Value type is u8. Valid range is 32-64. Default is 32.
- xlnx,include-dre	: Tells whether DMA h/w is configured with data
			  realignment engine(DRE) or not.

Optional properties (When USXGMII is in use):
- xlnx,usxgmii-rate	: USXGMII PHY speed - can be 10, 100, 1000, 2500,
			  5000 or 10000.

Optional properties for MRMAC:
- xlnx,phcindex		: Indicate the index of the physical hardware clock
			  to be used as per PTP clock connected to the given
			  MRMAC lane. Valid range is 0 to 3.
			  This property is deprecated.

Optional properties for MRMAC and 10G/25G:
- ptp-hardware-clock	: Indicate the xilinx PTP device node to read PTP clock
			  index(/dev/ptp0 etc).

NOTE: Time Sensitive Networking (TSN) related DT bindings are explained in [4].

[1] Documentation/devicetree/bindings/net/phy.txt
[2] Documentation/devicetree/bindings/net/ethernet.txt
[3] Documentation/devicetree/bindings/net/xilinx-phy.txt
[4] Documentation/devicetree/bindings/net/xilinx_tsn.txt

 - pcs-handle: 	  Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
		  modes, where "pcs-handle" should be used to point
		  to the PCS/PMA PHY, and "phy-handle" should point to an
		  external PHY if exists.

Example: AXI 1G/2.5G Ethernet Subsystem + AXIDMA

	axi_eth_0_dma: dma@80040000 {
			#dma-cells = <1>;
			compatible = "xlnx,eth-dma";
			xlnx,addrwidth = /bits/ 8 <32>;
			<snip>
	};

	axi_eth_0: ethernet@80000000 {
			axistream-connected = <&axi_eth_0_dma>;
			compatible = "xlnx,axi-ethernet-1.00.a";
			device_type = "network";
			interrupt-names = "interrupt";
			interrupt-parent = <&gic>;
			interrupts = <0 91 4>;
			phy-handle = <&phy2>;
			phy-mode = "sgmii";
			reg = <0x0 0x80000000 0x0 0x40000>;
			xlnx,include-dre ;
			xlnx,phy-type = <0x5>;
			xlnx,rxcsum = <0x0>;
			xlnx,rxmem = <0x1000>;
			xlnx,txcsum = <0x0>;
			axi_eth_0_mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				phy2: phy@2 {
					device_type = "ethernet-phy";
					reg = <2>;
				};
			};
	};

Example for MRMAC Ethernet subsystem with MCDMA:
	axi_mcdma_0: axi_mcdma@a4050000 {
			#dma-cells = <1>;
			compatible = "xlnx,axi-mcdma-1.1";
			xlnx,addrwidth = <0x20>;
			xlnx,include-dre;
			<snip>
	};

	gt_pll: gpio@a4000000 {
		reg = <0x0 0xa4000000 0x0 0x10000>;
		<snip>
	}

	gt_ctrl: gpio@a4010000 {
		reg = <0x0 0xa4010000 0x0 0x40000>;
		<snip>
	};

	mrmac_0: mrmac@80000000 {
		axistream-connected = <&axi_mcdma_0>;
		compatible = "xlnx,mrmac-ethernet-1.0";
		reg = <0x0 0xa4090000 0x0 0x1000>;
		xlnx,mrmac-rate = <10000>;
		xlnx,gtpll = <&gt_pll>;
		xlnx,gtctrl = <&gt_ctrl>;
		xlnx,gtlane = <0x0>;
		xlnx,rxmem = <0x8000>;
		ptp-hardware-clock = <&ptp_device>;
	};
