Xilinx VPSS Scaler
------------------
The Xilinx VPSS Scaler is a Video IP that supports up scaling,
down scaling and no scaling functionailty. This supports custom
resolution values between 0 to 4096.

Required properties:

- compatible: Must be "xlnx,vpss-scaler-2.2" or "xlnx,vpss-scaler".

- reg: Physical base address and length of registers set for the device.

- xlnx,num-hori-taps: The number of horizontal taps for scaling filter
  supported tap values are 2/4/6/8/10/12.

- xlnx,num-vert-taps: The number of vertical taps for scaling filter
  supported tap values are 2/4/6/8/10/12.

  A value of 2 represents bilinear filters. A value of 4 represents bicubic.
  Values 6, 8, 10, 12 represent polyphase filters.

- xlnx,pix-per-clk : The pixels per clock property of the IP.
  supported values are 1 and 2.

- reset-gpios: GPIO specifier to assert/de-assert the reset line.

- clocks: List of phandles to AXI Lite and Video clock

- clock-names: Must contain "aclk_ctrl" and "aclk_axis" in same order as clocks
  listed in clocks property.

- xlnx,max-width: Maximum number of pixels in a line.
  Valid range from 64 to 8192.

- xlnx,max-height: Maximum number of lines in a frame.
  Valid range from 64 to 4320.

Example:
	scaler@a0040000 {
		compatible = "xlnx,vpss-scaler";
		reg = <0x0 0xa0000000 0x0 0x40000>;
		reset-gpios = <&gpio 0x0 GPIO_ACTIVE_LOW>;
		xlnx,num-hori-taps = <8>;
		xlnx,num-vert-taps = <8>;
		xlnx,pix-per-clk = <2>;
		clock-names = "aclk_ctrl", "aclk_axis";
		clocks = <&misc_clk_0>, <&misc_clk_1>;
		xlnx,max-width = <3840>;
		xlnx,max-height = <2160>;
	}
