Device-Tree bindings for Xilinx SDI Tx subsystem

The IP core supports transmission of video data in SDI Tx protocol

Required properties:
 - compatible: Should be "xlnx,sdi-tx".
 - interrupts: Interrupt number.
 - interrupts-parent: phandle for interrupt controller.
 - reg: Base address and size of the IP core.
 - port: Logical block can be used / connected independently with
   external device. In the display controller port nodes, topology
   for entire pipeline should be described using the DT bindings defined in
   Documentation/devicetree/bindings/graph.txt.
   Minimum one port is required. At max, 2 ports are present.
   The reg index for AXI4 stream port is 0 and for ancillary data is 1.
 - clocks: List of phandles to AXI Lite, Video and SDI Tx Clock
 - clock-names: Must contain "s_axi_aclk", "video_in_clk" and "sdi_tx_clk"
   in same order as clocks listed in clocks property.
 - phy-reset-gpio: Specifier for a gpio that asserts GT phy

Optional properties:
 - xlnx,vpss: vpss phandle
   This handle is required only when VPSS is connected to SDI as bridge.
 - xlnx,tx-insert-c-str-st352: Insert ST352 payload in Chroma stream.
 - interrupt-names: Should be "sdi_tx_irq". This is only required when
   multiple interrupts are connected in the hardware design.
 - xlnx,qpll1enabled: boolean property present when the QPLL1 drives GT clock
   absent with QPLL0 drives GT clock
- xlnx,picxo_enabled: boolean property present when PICXO is present in design

Example:

	sdi_tx_subsystem@80000000 {
		compatible = "xlnx,sdi-tx";
		reg = <0x0 0x80000000 0x0 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <0 90 4>;
		interrupt-names = "sdi_tx_irq";
		#address-cells = <1>;
		#size-cells = <0>;
		xlnx,vpss = <&v_proc_ss_0>;
		clock-names = "s_axi_aclk", "video_in_clk", "sdi_tx_clk";
		clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>;
		phy-reset-gpio = <&axi_gpio_0 0 0 0>;
		xlnx,qpll1enabled;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			encoder_sdi_port: port@0 {
				reg = <0>;
				sdi_encoder: endpoint {
					remote-endpoint = <&pl_disp_crtc>;
				};
			};

			sdi_audio_port: port@1 {
				reg = <1>;
				sdi_audio_sink_port: endpoint {
					remote-endpoint = <&sditx_audio_embed_src_port>;
				};
			};
		};
	};
