Ð þía38\�(£\X$rockchip,rk3128-evbrockchip,rk3128 +!7Rockchip RK3128 Evaluation boardaliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000�/mmc@1021c000arm-pmuarm,cortex-a7-pmu0†LMNO‘cpus+¤rockchip,rk3036-smpcpu@f00²cpuarm,cortex-a7¾ÂÉÐäócpu@f01²cpuarm,cortex-a7¾ÉÐócpu@f02²cpuarm,cortex-a7¾ÉÐócpu@f03²cpuarm,cortex-a7¾ÉÐóopp-table-0operating-points-v2ûóopp-216000000 ßæ  ~ð~ð7Èœ@opp-408000000Q–  ~ð~ð7Èœ@opp-600000000#ÃF  ~ð~ð7Èœ@opp-696000000)|  à˜à˜7Èœ@opp-8160000000£,  g8g87È,œ@opp-1008000000<Ü  O€O€7Èœ@opp-1200000000G†Œ  7È7È7Èœ@display-subsystemrockchip,display-subsystem8 >disabledopp-table-1operating-points-v2ó opp-200000000 ë  à˜à˜Ðopp-300000000ᣠ ��Ðopp-400000000ׄ  Œ0Œ0Ðopp-480000000œ8  ÐÐÐtimerarm,armv7-timer0†   Ein6oscillator fixed-clockin6yxin24mŒó)sram@10080000 mmio-sram¾ + ™ smp-sram@0rockchip,rk3066-smp-sram¾gpu@10090000"rockchip,rk3128-maliarm,mali-400¾ H† gpgpmmupp0ppmmu0pp1ppmmu1ÂÕÕ °buscoreÐ Éx¼  >disabledsyscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd¾ power-controller!rockchip,rk3128-power-controllerÊ+ó power-domain@1¾˜ÂÆÖ¿ÑÇÔÌÏEr”ÍÓÀÁÒÕ¾zÞ Êpower-domain@2¾(ÂÅÎÄ͆ÞÊpower-domain@3¾ÂÕÞÊvideo-codec@10106000(rockchip,rk3128-vpurockchip,rk3066-vpu¾`†  vepuvdpu ÂÅÎÄÍ(°aclk_vdpuhclk_vdpuaclk_vepuhclk_vepuå¼ iommu@10106800rockchip,iommu¾h †CÂÄÎ °aclkiface¼ ìóvop@1010e000rockchip,rk3126-vop¾à † Â̾ϰaclk_vopdclk_vophclk_vopÉdef ùaxiahbdclk¼  >disabledport+óendpoint@0¾ó.endpoint@1¾ódsi@10110000*rockchip,rk3128-mipi-dsisnps,dw-mipi-dsi¾@ †!ÂE°pclkdphy¼ ɉùapb$ >disabledports+port@0¾endpointóport@1¾qos@1012d000rockchip,rk3128-qossyscon¾Ð óqos@1012e000rockchip,rk3128-qossyscon¾à óqos@1012f000rockchip,rk3128-qossyscon¾ð óqos@1012f080rockchip,rk3128-qossyscon¾ð€ ó qos@1012f100rockchip,rk3128-qossyscon¾ñ ó qos@1012f180rockchip,rk3128-qossyscon¾ñ€ ó qos@1012f200rockchip,rk3128-qossyscon¾ò óinterrupt-controller@10139000arm,cortex-a7-gic ¾� À à  † 1Fóusb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2¾ † ÂÚ°otgWotg_q€€€@  usb2-phy>okay�usb@101c0000 generic-ehci¾ † ÂÙusb>okayusb@101e0000 generic-ohci¾ † ÂÙusb>okayi2s@10200000(rockchip,rk3128-i2srockchip,rk3066-i2s¾  †DÂP»°i2s_clki2s_hclk› txrxª >disabledspdif@10204000,rockchip,rk3128-spdifrockchip,rk3066-spdif¾ @ †7ÂS¸ °mclkhclk›  tx»defaultɪ >disabledspi@1020c000 rockchip,sfc¾ À€ †2™߰clk_sfchclk_sfc >disabledmmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!@@ † ÂÈDrv°biuciuciu-driveciu-sample›  rx-txÓÞðÑ€ÉQùreset >disabledmmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!€@ † ÂÉEsw°biuciuciu-driveciu-sample›  rx-txÓÞðÑ€ÉRùreset >disabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!À@ † ÂËGuy°biuciuciu-driveciu-sample›  rx-txÓÞðÑ€ÉSùreset>okayì»default Éi2s@10220000(rockchip,rk3128-i2srockchip,rk3066-i2s¾" †ÂQ¼°i2s_clki2s_hclk› txrxö»defaultÉ ª >disablednand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfc¾P@ †ÂÅC°ahbnfc»default É!"#$%&'( >disabledclock-controller@20000000rockchip,rk3128-cru¾ Â)°xin24m$Œ.#g¸€ósyscon@20008000&rockchip,rk3128-grfsysconsimple-mfd¾ €+óusb2phy@17crockchip,rk3128-usb2phy¾| ÂŽ°phyclk yusb480m_phyšC*Œ>okayó*host-port †5  linestateZ>okayóotg-port$†#34 otg-bvalidotg-idlinestateZ>okayóhdmi@20034000rockchip,rk3128-inno-hdmi¾ @@ †-ÂG¾ °pclkref»default É+,-¼ ª >disabledports+port@0¾endpoint.óport@1¾phy@20038000rockchip,rk3128-dsi-dphy¾ €@”r °refpclkZ¼ É$ùapb >disabledótimer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer¾ @  †ÂaU °pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer¾ @  †ÂaV °pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer¾ @@  †;ÂaW °pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer¾ @`  †<ÂaX °pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer¾ @€  †=ÂaY °pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer¾ @   †>ÂaZ °pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt¾ À †"Â? >disabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Â^»defaultÉ/e >disabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Â^»defaultÉ0e >disabledpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm¾  Â^»defaultÉ1e >disabledpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ 0Â^»defaultÉ2e >disabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ ` †°i2cÂM»defaultÉ3+>okayrtc@51haoyu,hym8563¾QŒyxin32ki2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c¾   †°i2cÂN»defaultÉ4+ >disabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ à †°i2cÂO»defaultÉ5+ >disabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart¾  †in6ÂMU°baudclkapb_pclk› txrx»default É678p} >disabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart¾ @ †in6ÂNV°baudclkapb_pclk› txrx»defaultÉ9p} >disabledserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart¾ € †in6ÂOW°baudclkapb_pclk› txrx»defaultÉ:p} >disabledsaradc@2006c000rockchip,saradc¾ À †Â[>°saradcapb_pclkÉW ùsaradc-apb‡ >disabledi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c¾   †°i2cÂL»defaultÉ;+ >disabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi¾ @ †ÂAR°spiclkapb_pclk›  txrx»defaultÉ<=>?@+ >disableddma-controller@20078000arm,pl330arm,primecell¾ €@†™´Â °apb_pclkËóethernet@2008c000rockchip,rk3128-gmac¾ À@†89 macirqeth_wake_irq8Â~�‚€ÔoM°stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macÉ8 ùstmmaceth$Öä >disabledmdiosnps,dwmac-mdio+pinctrlrockchip,rk3128-pinctrl$+™gpio@2007c000rockchip,gpio-bank¾ À †$Â@ò1FóCgpio@20080000rockchip,gpio-bank¾  †%ÂAò1Fgpio@20084000rockchip,gpio-bank¾ @ †&ÂBò1FóEgpio@20088000rockchip,gpio-bank¾ € †'ÂCò1Fpcfg-pull-defaultóBpcfg-pull-none$óAemmcemmc-clk1Aóemmc-cmd1Bóemmc-cmd11Bemmc-pwr1Bemmc-bus11Bemmc-bus4@1BBBBemmc-bus8€1BBBBBBBBógmacrgmii-pinsð1B B B B BBBBBBBBBBBrmii-pins 1B B BBBBBBBBhdmihdmii2c-xfer 1AAó+hdmi-hpd1Aó,hdmi-cec1Aó-i2c0i2c0-xfer 1AAó;i2c1i2c1-xfer 1AAó3i2c2i2c2-xfer 1AAó4i2c3i2c3-xfer 1AAó5i2si2s-bus`1A A A A AAó i2s1-bus`1AAAAAAlcdclcdc-dclk1Alcdc-den1 Alcdc-hsync1 Alcdc-vsync1 Alcdc-rgb24à1 A AAAAAAAAAAAAAnfcflash-ale1Aó!flash-cle1Aó#flash-wrn1Aó(flash-rdn1Aó&flash-rdy1Aó'flash-cs01Aó$flash-dqs1Aó%flash-bus8€1AAAAAAAAó"pwm0pwm0-pin1Aó/pwm1pwm1-pin1Aó0pwm2pwm2-pin1Aó1pwm3pwm3-pin1Aó2sdiosdio-clk1Asdio-cmd1Bsdio-pwren1Bsdio-bus4@1BBBBsdmmcsdmmc-clk1Asdmmc-cmd1Bsdmmc-det1Bsdmmc-wp1Bsdmmc-pwren1Bsdmmc-bus4@1BBBBsfcsfc-bus2 1BBsfc-bus4@1BBBBsfc-clk1Asfc-cs01Bsfc-cs11Bspdifspdif-tx1Aóspi0spi0-clk1Bó>spi0-cs01 Bó?spi0-tx1 Bó<spi0-rx1 Bó=spi0-cs11 Bó@spi1-clk1Bspi1-cs01Bspi1-tx1Bspi1-rx1Bspi1-cs11Bspi2-clk1 Bspi2-cs01Bspi2-tx1 Bspi2-rx1 Buart0uart0-xfer 1BAó6uart0-cts1Aó7uart0-rts1Aó8uart1uart1-xfer 1 B Bó9uart1-cts1Auart1-rts1 Auart2uart2-xfer 1BAó:uart2-cts1Auart2-rts1Ausb-hosthost-vbus-drv1AóFusb-otgotg-vbus-drv1AóDchosen?/serial@20068000memory@60000000²memory¾`@regulator-vcc5v0-otgregulator-fixed KC»defaultÉD Pvcc5v0_otg_LK@wLK@óregulator-vcc5v0-hostregulator-fixed KE»defaultÉF Pvcc5v0_host�_LK@wLK@ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2mmc0interruptsinterrupt-affinityenable-methoddevice_typeregclocksresetsoperating-points-v2#cooling-cellsphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domains#power-domain-cellspm_qosiommus#iommu-cellsreset-namesremote-endpointphysphy-namesrockchip,grfinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevbus-supplydmasdma-names#sound-dai-cellspinctrl-namespinctrl-0fifo-depthmax-frequencybus-widthrockchip,playback-channels#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathgpioregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on