8(<Sony Xperia Z!sony,xperia-yugaqcom,apq8064,=handsetreserved-memoryJsmem@80000000Q U\ wcnss@8f000000QpU\Tcpuscpu@0 !qcom,kraitdqcom,kpss-acc-v1rcpuQ~\fcpu@1 !qcom,kraitdqcom,kpss-acc-v1rcpuQ~\hcpu@2 !qcom,kraitdqcom,kpss-acc-v1rcpuQ~ \jcpu@3 !qcom,kraitdqcom,kpss-acc-v1rcpuQ~  \ll2-cache!cache\idle-statescpu-spc#!qcom,idle-state-spcarm,idle-state \memory@0rmemoryQthermal-zonescpu0-thermal! 1tripstrip0>$JEpassivetrip1>J Ecriticalcpu1-thermal! 1ltripstrip0>$JEpassivetrip1>J Ecriticalcpu2-thermal! 1tripstrip0>$JEpassivetrip1>J Ecriticalcpu3-thermal! 1ltripstrip0>$JEpassivetrip1>J Ecriticalcpu-pmu!qcom,krait-pmu U clockscxo_board !fixed-clock`m$\/pxo_board !fixed-clock`m\sleep_clk !fixed-clock`m\smem !qcom,smem} smsm !qcom,smsm    @apps@0Q\^modem@1Q U&q6@2Q UYwcnss@3Q U\Sdsps@4Q Ufirmwarescm!qcom,scm-apq8064qcom,scm corereplicator !arm,coresight-static-replicator apb_pclkin-portsportendpoint\eout-portsport@0Qendpoint\_port@1Qendpoint\`socJ !simple-buspinctrl@800000!qcom,apq8064-pinctrlQ@/Z; UGdefaultU\sdcc1-default-state\Hclk-pins _sdc1_clkdscmd-pins _sdc1_cmdd data-pins _sdc1_datad sdcc3-default-state\Dclk-pins _sdc3_clkdscmd-pins _sdc3_cmdddata-pins _sdc3_datadsdc4-default-state*_gpio63gpio64gpio65gpio66gpio67gpio68sdc4\Ggsbi1-uart-2pins-state_gpio18gpio19gsbi1gsbi1-uart-4pins-state_gpio18gpio19gpio20gpio21gsbi1gsbi4-uart-pin-active-state\!rx-pins_gpio11gsbi4dstx-pins_gpio10gsbi4dsgsbi6-uart-2pins-state_gpio14gpio15gsbi6gsbi6-uart-4pins-state_gpio14gpio15gpio16gpio17gsbi6gsbi7-uart-2pins-state_gpio82gpio83gsbi7gsbi7_uart_4pins-state_gpio82gpio83gpio84gpio85gsbi7i2c1-default-state_gpio20gpio21gsbi1ds\i2c1-sleep-state_gpio20gpio21gpiods\i2c2-default-state_gpio24gpio25gsbi2ds\i2c2-sleep-state_gpio24gpio25gpiods\i2c3-default-state _gpio8gpio9gsbi3ds\i2c3-sleep-state _gpio8gpio9gpiods\ i2c4-default-state_gpio12gpio13gsbi4ds\"i2c4-sleep-state_gpio12gpio13gpiods\#i2c6-default-state_gpio16gpio17gsbi6ds\'i2c6-sleep-state_gpio16gpio17gpiods\(i2c7-default-state_gpio84gpio85gsbi7ds\)i2c7-sleep-state_gpio84gpio85gpiods\*spi5-default-state\%spi5-pins_gpio51gpio52gpio54gsbi5dsspi5-cs-pins_gpio53gpiodsspi5-sleep-state\&spi5-pins_gpio51gpio52gpio53gpio54gpiodriva-fm-active-state_gpio14gpio15riva_fm\Wriva-bt-active-state_gpio16gpio17riva_bt\Vriva-wlan-active-state#_gpio64gpio65gpio66gpio67gpio68 riva_wland\Uhdmi-pinctrl-state\Pddc-pins_gpio70gpio71hdmidhpd-pins_gpio72hdmidps-hold-default-state_gpio78ps_hold\gsbi5-uart-pin-active-state\$rx-pins_gpio52gsbi5dtx-pins_gpio51gsbi5dssdcc3-cd-pin-active-state_gpio26gpiods\Ehwmutex@1200600!qcom,sfpb-mutexQ \interrupt-controller@2000000!qcom,msm-qgic2Q \timer@200a0005!qcom,kpss-wdt-apq8064qcom,kpss-timerqcom,msm-timer$UQmsleepclock-controller@2088000!qcom,kpss-acc-v1Q pll8_votepxo acpu0_aux`\clock-controller@2098000!qcom,kpss-acc-v1Q  pll8_votepxo acpu1_aux`\clock-controller@20a8000!qcom,kpss-acc-v1Q  pll8_votepxo acpu2_aux`\clock-controller@20b8000!qcom,kpss-acc-v1Q  pll8_votepxo acpu3_aux`\ power-manager@2089000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2Q\regulator P power-manager@2099000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2Q \regulator P power-manager@20a9000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2Q \ regulator P power-manager@20b9000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2Q \ regulator P sps-sic-non-secure@12100000!sysconQ\gsbi@12440000  disabled!qcom,gsbi-v1.0.0QDifaceJserial@12450000%!qcom,msm-uartdm-v1.3qcom,msm-uartdmQE@ U coreiface  disabledi2c@12460000!qcom,i2c-qup-v1.1.1U+GdefaultsleepQF U coreiface  disabledgsbi@12480000  disabled!qcom,gsbi-v1.0.0QHifaceJi2c@124a0000!qcom,i2c-qup-v1.1.1QJU+Gdefaultsleep U coreiface  disabledgsbi@16200000  disabled!qcom,gsbi-v1.0.0Q ifaceJi2c@16280000!qcom,i2c-qup-v1.1.1U+ GdefaultsleepQ( U coreiface  disabledgsbi@16300000  disabled!qcom,gsbi-v1.0.0Q0ifaceJserial@16340000%!qcom,msm-uartdm-v1.3qcom,msm-uartdmQ40 UU!Gdefault coreiface  disabledi2c@16380000!qcom,i2c-qup-v1.1.1U"+#GdefaultsleepQ8 U coreiface  disabledgsbi@1a200000 okay!qcom,gsbi-v1.0.0Q ifaceJ5serial@1a240000%!qcom,msm-uartdm-v1.3qcom,msm-uartdmQ$  U coreiface okayGdefaultU$spi@1a280000!qcom,spi-qup-v1.1.1Q( UU%+&Gdefaultsleep coreiface  disabledgsbi@16500000  disabled!qcom,gsbi-v1.0.0QPifaceJserial@16540000%!qcom,msm-uartdm-v1.3qcom,msm-uartdmQTP U coreiface  disabledi2c@16580000!qcom,i2c-qup-v1.1.1U'+(GdefaultsleepQX U coreiface  disabledgsbi@16600000  disabled!qcom,gsbi-v1.0.0Q`ifaceJserial@16640000%!qcom,msm-uartdm-v1.3qcom,msm-uartdmQd` U coreiface  disabledi2c@16680000!qcom,i2c-qup-v1.1.1U)+*GdefaultsleepQh U coreiface  disabledrng@1a500000 !qcom,prngQPcoressbi@c00000 !qcom,ssbiQ ?pmic-arbiterpmic !qcom,pm8821 TLmpps@50!qcom,pm8821-mppqcom,ssbi-mppQP;/+\+ssbi@500000 !qcom,ssbiQP ?pmic-arbiterpmic !qcom,pm8921 TJ\,pwrkey@1c!qcom,pm8921-pwrkeyQT,2,3h= mpps@50!qcom,pm8921-mppqcom,ssbi-mppQP;/- \-rtc@11d!qcom,pm8921-rtcQ T,'qkeypad@148!qcom,pm8921-keypadQHT,J,Kh el  disabledgpio@150 !qcom,pm8921-gpioqcom,ssbi-gpioQP/.,;\.gpio-keys-active-state_gpio3gpio4gpio29gpio35normal\oxoadc@197!qcom,pm8921-adcQ T,N\nadc-channel@0Qadc-channel@1Qadc-channel@2Qadc-channel@4Qadc-channel@8Qadc-channel@9Q adc-channel@aQ adc-channel@bQ adc-channel@cQ adc-channel@dQ adc-channel@eQadc-channel@fQefuse@700000 !qcom,apq8064-qfpromqcom,qfpromQpcalib@404Q\1backup_calib@414Q\2clock-controller@900000!qcom,gcc-apq8064sysconQ@`/0 cxopxopll4\thermal-sensor!qcom,msm8960-tsens12calibcalib_backup U$uplow4 B\ clock-controller@28000000!qcom,lcc-apq8064Q(`$pxopll4_votemi2s_codec_clkcodec_i2s_mic_codec_clkspare_i2s_mic_codec_clkcodec_i2s_spkr_codec_clkspare_i2s_spkr_codec_clkpcm_codec_clk\0clock-controller@4000000!qcom,mmcc-apq8064Q`X833445Cpxopll3pll8_votedsi1plldsi1pllbytedsi2plldsi2pllbytehdmipll\Kclock-controller@2011000+!qcom,kpss-gcc-apq8064qcom,kpss-gccsysconQ pll8_votepxo`\rpm@108000!qcom,rpm-apq8064Q l$U$ackerrwakeupclock-controller!qcom,rpmcc-apq8064qcom,rpmcc`/pxocxo\regulators!qcom,rpm-pm8921-regulatorsu666768899s1(('0\8s2  'j\Zs3 0'I>\Xs4w@w@'jB\6s7  '0\9s8!!'jl1l2OOl3..\<l4w@w@\=l5-p-p\Jl6-p-p\7l7:-pl8**l9--l10,@ ,@ \[l11--l12OOl14w@w@l15w@-pl16**l17l18OOl21l22'@'@l23w@w@l24 q0\Yl25l27l28l29lvs1lvs2\\lvs3lvs4lvs5lvs6lvs7usb-switchhdmi-switchncpw@w@'jusb@12500000 !qcom,ci-hdrcQPP Ud~ coreifaceRbw@~coreulpi:usb-phy okayotg\;ulpiphy(!qcom,usb-hs-phy-apq8064qcom,usb-hs-phy/ sleeprefw;~por<=\:usb@12520000 !qcom,ci-hdrcQRR U)' coreifaceR)bwd~coreulpi>usb-phy  disabled\?ulpiphy(!qcom,usb-hs-phy-apq8064qcom,usb-hs-phy/ sleeprefw?~por\>usb@12530000 !qcom,ci-hdrcQSS U,* coreifaceR,bwe~coreulpi@usb-phy  disabled\Aulpiphy(!qcom,usb-hs-phy-apq8064qcom,usb-hs-phy/ sleeprefwA~por\@phy@1b400000!qcom,apq8064-sata-phy  disabledQ@-cfg\Bsata@29000000!qcom,apq8064-ahcigeneric-ahci  disabledQ) U(;.%slave_ifaceifacecorerxoobpmaliveRbB sata-phymmc@12180000!arm,pl18xarm,primecell okayQ  Ufzpmclkapb_pclk"4 qBKCCPtxrxZ7 fGdefaultUDEdma-controller@12182000!qcom,bam-v1.3.0Q  U`pbam_clkoz\Cmmc@121c0000!arm,pl18xarm,primecell  disabledQ  Ue{qmclkapb_pclk"4lKFFPtxrxGdefaultUGdma-controller@121c2000!qcom,bam-v1.3.0Q  U_qbam_clkoz\Fmmc@12400000 okay!arm,pl18xarm,primecellGdefaultUHQ@  Uhxnmclkapb_pclk4"KIIPtxrxZJ6dma-controller@12402000!qcom,bam-v1.3.0Q@  Ubnbam_clkoz\Isyscon@1a400000!qcom,tcsr-apq8064sysconQ@\gpu@4300000!qcom,adreno-320.2qcom,adrenoQ0kgsl_3d0_reg_memory UP $kgsl_3d0_irqcoreifacememmem_iface KGKK!KLLLLLLLLLL L L L L LLLLLLLLLLLLLLLLLLMMMMMMMMMM M M M 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disabledpcie@0rpciQJhdmi-tx@4a00000!qcom,hdmi-tx-8960GdefaultUPQcore_physical UOK>K Kcoremaster_ifaceslave_iface5  disabledportsport@0Qendpointport@1Qendpointphy@4a00400!qcom,hdmi-phy-8960Q`hdmi_phyhdmi_pllK slave_iface`  disabled\5display-controller@5100000 !qcom,mdp4Q UK0KMKKKNK_K`3core_clkiface_clkbus_clklut_clkhdmi_clktv_clk QQRRportsport@0Qendpointport@1Qendpointport@2Qendpointport@3Qendpointriva-pil@3200800!qcom,riva-pilQ   @ ccudxepmuTS $wdogfatal}T okayGdefault UUVWHXUYb6\]iris !qcom,wcn3660/xoo=|Z[\smd-edge U lrivawcnss !qcom,wcnss WCNSS_CTRL]bluetooth!qcom,wcnss-btwifi!qcom,wcnss-wlanU$txrx^ ^ tx-enabletx-rings-emptyetb@1a01000"!arm,coresight-etb10arm,primecellQ apb_pclkin-portsportendpoint_\tpiu@1a03000!!arm,coresight-tpiuarm,primecellQ0 apb_pclkin-portsportendpoint`\funnel@1a04000+!arm,coresight-dynamic-funnelarm,primecellQ@ apb_pclkin-portsport@0Qendpointa\gport@1Qendpointb\iport@4Qendpointc\kport@5Qendpointd\mout-portsportendpointe\etm@1a1c000"!arm,coresight-etm3xarm,primecellQ apb_pclkfout-portsportendpointg\aetm@1a1d000"!arm,coresight-etm3xarm,primecellQ apb_pclkhout-portsportendpointi\betm@1a1e000"!arm,coresight-etm3xarm,primecellQ apb_pclkjout-portsportendpointk\cetm@1a1f000"!arm,coresight-etm3xarm,primecellQ apb_pclklout-portsportendpointm\diio-hwmon !iio-hwmonTnnnn n n naliases# /soc/gsbi@1a200000/serial@1a240000chosenserial0:115200n8gpio-keys !gpio-keysGdefaultUokey-camera-focus camera_focus i. 1key-camera-snapshotcamera_snapshot i. 1key-volume-down volume_down i. 1rkey-volume-up volume_up i.# 1s #address-cells#size-cellsmodelcompatibleinterrupt-parentchassis-typerangesregno-mapphandleenable-methoddevice_typenext-level-cacheqcom,accqcom,sawcpu-idle-statescache-levelcache-unifiedentry-latency-usexit-latency-usmin-residency-uspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresisinterrupts#clock-cellsclock-frequencymemory-regionhwlocksqcom,ipc-1qcom,ipc-2qcom,ipc-3qcom,ipc-4#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsclocksclock-namesremote-endpointgpio-controllergpio-ranges#gpio-cellspinctrl-namespinctrl-0pinsdrive-strengthbias-disablebias-pull-upfunctionoutput-highbias-pull-down#hwlock-cellscpu-offsetclock-output-namesregulator-min-microvoltregulator-max-microvoltstatuscell-indexsyscon-tcsrpinctrl-1qcom,modeqcom,controller-typeinterrupts-extendeddebounceallow-set-timescan-delayrow-holddrive-push-pullinput-enablepower-sourceqcom,drive-strengthqcom,pull-up-strength#io-channel-cells#reset-cellsnvmem-cellsnvmem-cell-namesinterrupt-names#qcom,sensors#thermal-sensor-cells#power-domain-cellsqcom,ipcvin_l1_l2_l12_l18-supplyvin_lvs_1_3_6-supplyvin_lvs_4_5_7-supplyvin_ncp-supplyvin_lvs2-supplyvin_l24-supplyvin_l25-supplyvin_l27-supplyvin_l28-supplyregulator-always-onqcom,switch-mode-frequencyqcom,force-modeassigned-clocksassigned-clock-ratesresetsreset-namesphy_typeahb-burst-configphysphy-namesdr_mode#phy-cellsv3p3-supplyv1p8-supplyports-implementedarm,primecell-periphidbus-widthcap-sd-highspeedcap-mmc-highspeedmax-frequencyno-1-8-vdmasdma-namesvmmc-supplycd-gpios#dma-cellsqcom,eenon-removablevqmmc-supplyreg-namesiommusoperating-points-v2opp-hzassigned-clock-parentssyscon-sfpb#iommu-cellsqcom,ncblinux,pci-domainbus-rangenum-lanesinterrupt-map-maskinterrupt-mapvddcx-supplyvddmx-supplyvddpx-supplyvddxo-supplyvddrfa-supplyvddpa-supplyvdddig-supplyqcom,smd-edgelabelqcom,smd-channelsqcom,mmioqcom,smem-statesqcom,smem-state-namescpuio-channelsserial0stdout-pathlinux,input-typelinux,code