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ffff800080806148 t simple_pm_bus_resume
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ffff80008080c008 t phy_axg_pcie_power_on
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ffff80008080c148 t phy_axg_mipi_pcie_analog_probe
ffff80008080c270 t phy_dsi_analog_disable
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ffff80008080c788 t phy_meson_axg_mipi_dphy_configure
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ffff80008080f008 T pinctrl_dev_get_name
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ffff80008098aae8 t hi3798cv200_crg_probe
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ffff800080991ba8 t clk_mt6779_top_probe
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ffff8000809921f0 t clk_mt6795_infracfg_probe
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ffff800080992f68 t clk_mt8186_apmixed_remove
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ffff800080994c08 T meson_clk_hw_get
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ffff800080998668 t armada_3700_xtal_clock_remove
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ffff800080998b08 t armada_3700_periph_clock_resume
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ffff800080998c28 t armada_3700_periph_clock_probe
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ffff80008099f570 t rockchip_mmc_set_phase
ffff80008099f708 t rockchip_mmc_clk_rate_notify
ffff80008099f7d8 T rockchip_clk_register_mmc
ffff80008099f968 t rockchip_muxgrf_get_parent
ffff80008099fa28 t rockchip_muxgrf_set_parent
ffff80008099fae8 T rockchip_clk_register_muxgrf
ffff80008099fc68 t rockchip_ddrclk_get_parent
ffff80008099fcc8 t rockchip_ddrclk_sip_set_rate
ffff80008099fdb8 t rockchip_ddrclk_sip_determine_rate
ffff80008099fe88 t rockchip_ddrclk_sip_recalc_rate
ffff80008099ff48 T rockchip_clk_register_ddrclk
ffff8000809a0108 t rk_clk_gate_link_probe
ffff8000809a02e8 t rockchip_softrst_deassert
ffff8000809a0408 T rockchip_register_softrst_lut
ffff8000809a0508 t rockchip_softrst_assert
ffff8000809a0628 T rk3528_rst_init
ffff8000809a0688 t clk_rk3562_probe
ffff8000809a0708 T rk3562_rst_init
ffff8000809a0768 t clk_rk3576_probe
ffff8000809a07e8 T rk3576_rst_init
ffff8000809a0848 t clk_rk3588_probe
ffff8000809a0908 T rk3588_rst_init
ffff8000809a0968 t samsung_clk_resume
ffff8000809a09f0 T samsung_clk_save
ffff8000809a0a50 t samsung_clk_suspend
ffff8000809a0b08 T samsung_clk_restore
ffff8000809a0b68 T samsung_clk_alloc_reg_dump
ffff8000809a0c28 T samsung_clk_add_lookup
ffff8000809a0c58 T samsung_clk_extended_sleep_init
ffff8000809a0d68 t samsung_pll_determine_rate
ffff8000809a0de8 t samsung_pll_lock_wait
ffff8000809a0ec8 t samsung_pll3xxx_disable
ffff8000809a0f08 t samsung_pll35xx_recalc_rate
ffff8000809a0f48 t samsung_pll2550xx_recalc_rate
ffff8000809a0f88 t samsung_pll2126_recalc_rate
ffff8000809a0fd0 t samsung_pll3000_recalc_rate
ffff8000809a1018 t samsung_pll3xxx_enable
ffff8000809a1088 t samsung_pll2550x_recalc_rate
ffff8000809a10d0 t samsung_pll45xx_recalc_rate
ffff8000809a1128 t samsung_pll6552_recalc_rate
ffff8000809a11a8 t samsung_pll0822x_recalc_rate
ffff8000809a1248 t samsung_pll36xx_recalc_rate
ffff8000809a1298 t samsung_pll0831x_recalc_rate
ffff8000809a12e8 t samsung_pll2650x_recalc_rate
ffff8000809a1348 t samsung_pll6553_recalc_rate
ffff8000809a13a8 t samsung_pll1031x_recalc_rate
ffff8000809a1408 t samsung_pll2650xx_recalc_rate
ffff8000809a1468 t samsung_pll531x_recalc_rate
ffff8000809a14d0 t samsung_pll46xx_recalc_rate
ffff8000809a15d8 t samsung_pll2550xx_set_rate
ffff8000809a1728 t samsung_pll0822x_set_rate
ffff8000809a1890 t samsung_pll2650x_set_rate
ffff8000809a19b0 t samsung_pll2650xx_set_rate
ffff8000809a1ad0 t samsung_pll35xx_set_rate
ffff8000809a1ca8 t samsung_pll0831x_set_rate
ffff8000809a1e28 t samsung_pll36xx_set_rate
ffff8000809a2018 t samsung_pll45xx_set_rate
ffff8000809a21d8 t samsung_pll1031x_set_rate
ffff8000809a2388 t samsung_pll46xx_set_rate
ffff8000809a2628 t exynos_cpuclk_recalc_rate
ffff8000809a2648 t exynos_cpuclk_notifier_cb
ffff8000809a2708 t exynos850_alt_parent_set_max_rate
ffff8000809a27e8 t exynos_cpuclk_determine_rate
ffff8000809a2848 t wait_until_divider_stable
ffff8000809a2908 t exynos_set_safe_div.isra.0
ffff8000809a29a8 t wait_until_mux_stable
ffff8000809a2a88 t exynos5433_cpuclk_post_rate_change
ffff8000809a2b58 t exynos_cpuclk_post_rate_change
ffff8000809a2ca8 t exynos850_cpuclk_post_rate_change
ffff8000809a2de8 t exynos5433_cpuclk_pre_rate_change
ffff8000809a2fc8 t exynos850_cpuclk_pre_rate_change
ffff8000809a31d8 t exynos_cpuclk_pre_rate_change
ffff8000809a3468 t exynos_clkout_suspend
ffff8000809a34b0 t exynos_clkout_resume
ffff8000809a34e8 t exynos_clkout_remove
ffff8000809a3548 t exynos_clkout_probe
ffff8000809a38c8 T exynos_arm64_cmu_suspend
ffff8000809a39f0 T exynos_arm64_cmu_resume
ffff8000809a3b28 T ccu_pll_notifier_register
ffff8000809a3b78 t devm_sunxi_ccu_release
ffff8000809a3c10 t sunxi_ccu_probe
ffff8000809a3ed0 T devm_sunxi_ccu_probe
ffff8000809a3fc8 t ccu_helper_wait_for_lock.part.0
ffff8000809a40a8 T ccu_helper_wait_for_lock
ffff8000809a4108 t ccu_pll_notifier_cb
ffff8000809a41b0 T ccu_is_better_rate
ffff8000809a42a8 T of_sunxi_ccu_probe
ffff8000809a4368 T sunxi_ccu_set_mmc_timing_mode
ffff8000809a4430 T sunxi_ccu_get_mmc_timing_mode
ffff8000809a44a8 t ccu_reset_assert
ffff8000809a4568 t ccu_reset_status
ffff8000809a45c8 t ccu_reset_deassert
ffff8000809a4688 t ccu_reset_reset
ffff8000809a4708 t ccu_div_set_rate
ffff8000809a4828 t ccu_div_get_parent
ffff8000809a4868 t ccu_div_set_parent
ffff8000809a48b0 t ccu_div_determine_rate
ffff8000809a4910 t ccu_div_round_rate
ffff8000809a49a8 t ccu_div_is_enabled
ffff8000809a49e8 t ccu_div_disable
ffff8000809a4a30 t ccu_div_enable
ffff8000809a4a70 t ccu_div_recalc_rate
ffff8000809a4b68 T ccu_frac_helper_has_rate
ffff8000809a4bc8 T ccu_frac_helper_read_rate
ffff8000809a4d48 T ccu_frac_helper_set_rate
ffff8000809a4e68 T ccu_frac_helper_is_enabled
ffff8000809a4ec8 T ccu_frac_helper_disable
ffff8000809a4fa8 T ccu_frac_helper_enable
ffff8000809a50a8 t ccu_gate_recalc_rate
ffff8000809a50d8 t ccu_gate_set_rate
ffff8000809a50f0 t ccu_gate_determine_rate
ffff8000809a51c8 t ccu_gate_is_enabled
ffff8000809a5228 t ccu_gate_helper_enable.part.0
ffff8000809a52d8 T ccu_gate_helper_enable
ffff8000809a5330 t ccu_gate_enable
ffff8000809a5390 t ccu_gate_helper_disable.part.0
ffff8000809a5448 T ccu_gate_helper_disable
ffff8000809a54a8 t ccu_gate_disable
ffff8000809a5508 T ccu_gate_helper_is_enabled
ffff8000809a5588 t ccu_mux_is_enabled
ffff8000809a55c8 t ccu_mux_disable
ffff8000809a5610 t ccu_mux_enable
ffff8000809a5650 T ccu_mux_notifier_register
ffff8000809a5698 t ccu_mux_get_prediv
ffff8000809a5808 T ccu_mux_helper_apply_prediv
ffff8000809a5858 t ccu_mux_recalc_rate
ffff8000809a58b8 T ccu_mux_helper_determine_rate
ffff8000809a5af8 t ccu_mux_determine_rate
ffff8000809a5b68 T ccu_mux_helper_get_parent
ffff8000809a5c68 t ccu_mux_get_parent
ffff8000809a5ca8 T ccu_mux_helper_set_parent
ffff8000809a5db0 t ccu_mux_set_parent
ffff8000809a5e08 t ccu_mux_notifier_cb
ffff8000809a5f08 t ccu_mult_round_rate
ffff8000809a5f78 t ccu_mult_set_rate
ffff8000809a6148 t ccu_mult_get_parent
ffff8000809a6188 t ccu_mult_set_parent
ffff8000809a61d0 t ccu_mult_determine_rate
ffff8000809a6230 t ccu_mult_is_enabled
ffff8000809a6270 t ccu_mult_disable
ffff8000809a62b8 t ccu_mult_enable
ffff8000809a62f8 t ccu_mult_recalc_rate
ffff8000809a6408 t ccu_phase_set_phase
ffff8000809a6548 t ccu_phase_get_phase
ffff8000809a6648 T ccu_sdm_helper_get_factors
ffff8000809a66f8 T ccu_sdm_helper_has_rate
ffff8000809a6768 T ccu_sdm_helper_is_enabled
ffff8000809a6808 T ccu_sdm_helper_read_rate
ffff8000809a6988 T ccu_sdm_helper_enable
ffff8000809a6b18 T ccu_sdm_helper_disable
ffff8000809a6c48 t ccu_nk_set_rate
ffff8000809a6e78 t ccu_nk_is_enabled
ffff8000809a6eb8 t ccu_nk_disable
ffff8000809a6f08 t ccu_nk_enable
ffff8000809a6f48 t ccu_nk_determine_rate
ffff8000809a7088 t ccu_nk_recalc_rate
ffff8000809a7148 t ccu_nkm_get_parent
ffff8000809a7188 t ccu_nkm_set_parent
ffff8000809a71d0 t ccu_nkm_determine_rate
ffff8000809a7230 t ccu_nkm_is_enabled
ffff8000809a7270 t ccu_nkm_disable
ffff8000809a72b8 t ccu_nkm_enable
ffff8000809a72f8 t ccu_nkm_find_best.constprop.0
ffff8000809a7488 t ccu_nkm_set_rate
ffff8000809a76e8 t ccu_nkm_round_rate
ffff8000809a7a18 t ccu_nkm_recalc_rate
ffff8000809a7b08 t ccu_nkmp_is_enabled
ffff8000809a7b48 t ccu_nkmp_disable
ffff8000809a7b90 t ccu_nkmp_enable
ffff8000809a7bd0 t ccu_nkmp_set_rate
ffff8000809a7fd8 t ccu_nkmp_recalc_rate
ffff8000809a80e8 t ccu_nkmp_determine_rate
ffff8000809a83a8 t ccu_nm_determine_rate
ffff8000809a8638 t ccu_nm_is_enabled
ffff8000809a8678 t ccu_nm_disable
ffff8000809a86c8 t ccu_nm_enable
ffff8000809a8708 t ccu_nm_recalc_rate
ffff8000809a88a8 t ccu_nm_set_rate
ffff8000809a8c88 t ccu_mp_get_parent
ffff8000809a8cc8 t ccu_mp_set_parent
ffff8000809a8d10 t ccu_mp_determine_rate
ffff8000809a8d70 t ccu_mp_round_rate
ffff8000809a9150 t ccu_mp_is_enabled
ffff8000809a9190 t ccu_mp_disable
ffff8000809a91d8 t ccu_mp_enable
ffff8000809a9218 t ccu_mp_set_rate
ffff8000809a94b0 t ccu_mp_mmc_set_rate
ffff8000809a9528 t ccu_mp_mmc_determine_rate
ffff8000809a9628 t ccu_mp_recalc_rate
ffff8000809a9718 t ccu_mp_mmc_recalc_rate
ffff8000809a97a8 t sun50i_a64_ccu_probe
ffff8000809a98c8 t sun50i_a100_ccu_probe
ffff8000809a9ae8 t sun50i_a100_r_ccu_probe
ffff8000809a9b68 t sun50i_h6_ccu_probe
ffff8000809a9de8 t sun50i_h6_r_ccu_probe
ffff8000809a9e88 t sun50i_h616_ccu_probe
ffff8000809aa0c8 t sun55i_a523_ccu_probe
ffff8000809aa1a8 t sun55i_a523_mcu_ccu_probe
ffff8000809aa248 t sun55i_a523_r_ccu_probe
ffff8000809aa2c8 t ccu_iosc_recalc_accuracy
ffff8000809aa2e8 t ccu_iosc_is_enabled
ffff8000809aa328 t ccu_iosc_disable
ffff8000809aa370 t ccu_iosc_enable
ffff8000809aa3b0 t ccu_iosc_32k_recalc_rate
ffff8000809aa430 t ccu_iosc_32k_prepare
ffff8000809aa490 t ccu_iosc_32k_unprepare
ffff8000809aa508 t ccu_iosc_recalc_rate
ffff8000809aa568 t ccu_iosc_32k_recalc_accuracy
ffff8000809aa5c8 T sun6i_rtc_ccu_probe
ffff8000809aa748 t sun8i_h3_ccu_probe
ffff8000809aa868 t sunxi_de2_clk_probe
ffff8000809aab68 t sun8i_r_ccu_probe
ffff8000809aac08 t tegra_clk_rst_deassert
ffff8000809aace8 t tegra_clk_rst_assert
ffff8000809aadc8 t tegra_clk_rst_reset
ffff8000809aae28 T get_reg_bank
ffff8000809aae88 T tegra_clk_set_pllp_out_cpu
ffff8000809aaed8 T tegra_clk_periph_suspend
ffff8000809aaf78 T tegra_clk_periph_resume
ffff8000809ab0a8 T tegra_init_from_table
ffff8000809ab278 T tegra_register_devclks
ffff8000809ab378 T tegra_clk_dev_register
ffff8000809ab528 t clk_sync_source_recalc_rate
ffff8000809ab548 t clk_sync_source_determine_rate
ffff8000809ab588 t clk_sync_source_set_rate
ffff8000809ab5a8 T tegra_clk_register_sync_source
ffff8000809ab6c0 t pm_runtime_put
ffff8000809ab6f0 t pm_runtime_resume_and_get
ffff8000809ab7a8 t tegra_clock_set_pd_state.isra.0
ffff8000809ab8a8 t tegra_clock_probe
ffff8000809aba68 t tegra_clock_change_notify
ffff8000809abb68 t dfll_clk_is_enabled
ffff8000809abb88 t dfll_clk_recalc_rate
ffff8000809abba8 t attr_enable_get
ffff8000809abbd8 t attr_lock_get
ffff8000809abc08 T tegra_dfll_runtime_resume
ffff8000809abcf0 T tegra_dfll_runtime_suspend
ffff8000809abd48 T tegra_dfll_suspend
ffff8000809abdc8 t dfll_calculate_rate_request
ffff8000809abfe8 t dfll_clk_determine_rate
ffff8000809ac070 t find_vdd_map_entry_exact
ffff8000809ac188 t attr_registers_open
ffff8000809ac1d8 t rate_fops_open
ffff8000809ac238 t lock_fops_open
ffff8000809ac298 t enable_fops_open
ffff8000809ac2f8 T tegra_dfll_unregister
ffff8000809ac3c8 t attr_registers_show
ffff8000809ac5a8 t dfll_tune_low
ffff8000809ac638 t dfll_set_default_params.constprop.0
ffff8000809ac6f0 t dfll_enable
ffff8000809ac788 t dfll_disable
ffff8000809ac818 t attr_enable_set
ffff8000809ac870 t dfll_set_frequency_request.isra.0
ffff8000809ac8e8 t dfll_clk_set_rate
ffff8000809aca28 t attr_rate_set
ffff8000809acb50 t attr_rate_get
ffff8000809acbc8 t dfll_unlock
ffff8000809acd38 t dfll_clk_disable
ffff8000809acda8 t dfll_lock
ffff8000809acf50 t dfll_clk_enable
ffff8000809acfe8 t attr_lock_set
ffff8000809ad048 t dfll_init_out_if
ffff8000809ad270 T tegra_dfll_resume
ffff8000809ad348 T tegra_dfll_register
ffff8000809ae3e8 t clk_frac_div_determine_rate
ffff8000809ae4d8 t clk_frac_div_set_rate
ffff8000809ae5e8 t clk_divider_restore_context
ffff8000809ae658 t clk_frac_div_recalc_rate
ffff8000809ae6d8 T tegra_clk_register_divider
ffff8000809ae848 T tegra_clk_register_mc
ffff8000809ae8e8 t clk_periph_get_parent
ffff8000809ae948 t clk_periph_set_parent
ffff8000809ae9a8 t clk_periph_recalc_rate
ffff8000809aea08 t clk_periph_determine_rate
ffff8000809aea68 t clk_periph_set_rate
ffff8000809aeac8 t clk_periph_is_enabled
ffff8000809aeb28 t clk_periph_enable
ffff8000809aeb88 t clk_periph_disable
ffff8000809aebd0 t clk_periph_disable_unused
ffff8000809aec18 t clk_periph_restore_context
ffff8000809aecd8 T tegra_clk_register_periph
ffff8000809aee90 T tegra_clk_register_periph_nodiv
ffff8000809aefd0 T tegra_clk_register_periph_data
ffff8000809af188 t tegra_clk_periph_fixed_enable
ffff8000809af1c8 t tegra_clk_periph_fixed_disable
ffff8000809af208 t tegra_clk_periph_fixed_recalc_rate
ffff8000809af230 t tegra_clk_periph_fixed_is_enabled
ffff8000809af2c8 T tegra_clk_register_periph_fixed
ffff8000809af448 t clk_periph_disable
ffff8000809af550 t clk_periph_enable
ffff8000809af670 t clk_periph_disable_unused
ffff8000809af750 t clk_periph_is_enabled
ffff8000809af7e8 T tegra_clk_register_periph_gate
ffff8000809af9a8 t _calc_rate
ffff8000809afc88 t _tegra_clk_register_pll
ffff8000809afdb8 t _get_table_rate
ffff8000809afeb8 t clk_pll_determine_rate
ffff8000809affc8 t clk_pllre_determine_rate
ffff8000809b0090 t clk_pll_wait_for_lock
ffff8000809b0190 t _calc_dynamic_ramp_rate
ffff8000809b02d0 t _pll_ramp_calc_pll
ffff8000809b03c8 t clk_pll_ramp_determine_rate
ffff8000809b04f8 t clk_plle_tegra210_is_enabled
ffff8000809b0528 t _pllcx_update_dynamic_coef
ffff8000809b0648 t clk_plle_recalc_rate
ffff8000809b06f8 t _clk_plle_tegra_init_parent.isra.0
ffff8000809b07e8 t tegra_clk_plle_t210_restore_context
ffff8000809b0830 t clk_pll_is_enabled
ffff8000809b0890 t clk_plle_tegra210_disable
ffff8000809b0968 t _clk_pll_disable
ffff8000809b0a88 t clk_pll_disable
ffff8000809b0b30 t clk_plle_tegra114_disable
ffff8000809b0bd0 t clk_pllc_disable
ffff8000809b0c70 t _clk_pll_enable
ffff8000809b0df8 t clk_pllc_enable
ffff8000809b0f28 t clk_pllu_enable
ffff8000809b1188 t clk_pllu_tegra114_enable
ffff8000809b1458 t clk_pll_enable
ffff8000809b1550 t clk_plle_tegra114_enable
ffff8000809b18c8 t _update_pll_mnp
ffff8000809b1b18 t clk_plle_tegra210_enable
ffff8000809b1de8 t _get_pll_mnp
ffff8000809b1ff8 t clk_pllre_recalc_rate
ffff8000809b2088 t clk_pllre_set_rate
ffff8000809b2228 t _program_pll
ffff8000809b24b0 t clk_pll_set_rate
ffff8000809b26b0 t tegra_clk_pll_restore_context
ffff8000809b2790 t clk_pllxc_set_rate
ffff8000809b28c8 t clk_pllc_set_rate
ffff8000809b2a88 t clk_pll_recalc_rate
ffff8000809b2c68 t clk_plle_enable
ffff8000809b2fb0 T tegra_pll_wait_for_lock
ffff8000809b2fe8 T tegra_pll_p_div_to_hw
ffff8000809b3048 T tegra_pll_get_fixed_mdiv
ffff8000809b30b0 T tegra_clk_register_pll
ffff8000809b31d0 T tegra_clk_register_plle
ffff8000809b3310 T tegra_clk_register_pllu
ffff8000809b3428 T tegra_clk_register_pllxc
ffff8000809b36b0 T tegra_clk_register_pllre
ffff8000809b38c8 T tegra_clk_register_pllm
ffff8000809b3a70 T tegra_clk_register_pllc
ffff8000809b3d70 T tegra_clk_register_plle_tegra114
ffff8000809b3e88 T tegra_clk_register_pllu_tegra114
ffff8000809b3f98 T tegra_clk_register_pllss
ffff8000809b42c8 T tegra_clk_register_pllre_tegra210
ffff8000809b4410 T tegra_clk_register_plle_tegra210
ffff8000809b4528 T tegra_clk_register_pllc_tegra210
ffff8000809b46c8 T tegra_clk_register_pllss_tegra210
ffff8000809b4898 T tegra_clk_register_pllmb
ffff8000809b4bc8 t clk_pll_out_disable
ffff8000809b4c70 t clk_pll_out_is_enabled
ffff8000809b4cb0 t clk_pll_out_enable
ffff8000809b4d58 t tegra_clk_pll_out_restore_context
ffff8000809b4dd0 T tegra_clk_register_pll_out
ffff8000809b4f48 t clk_sdmmc_mux_is_enabled
ffff8000809b4fa8 t clk_sdmmc_mux_enable
ffff8000809b5008 t clk_sdmmc_mux_disable
ffff8000809b5050 t clk_sdmmc_mux_disable_unused
ffff8000809b5098 t clk_sdmmc_mux_determine_rate
ffff8000809b5198 t clk_sdmmc_mux_get_parent
ffff8000809b5270 t clk_sdmmc_mux_set_rate
ffff8000809b5368 t clk_sdmmc_mux_recalc_rate
ffff8000809b53a8 t clk_sdmmc_mux_set_parent
ffff8000809b5408 t clk_sdmmc_mux_restore_context
ffff8000809b54c8 T tegra_clk_register_sdmmc_mux_div
ffff8000809b5668 t clk_super_determine_rate
ffff8000809b56c8 t clk_super_recalc_rate
ffff8000809b5728 t clk_super_set_rate
ffff8000809b5788 t clk_super_get_parent
ffff8000809b5828 t clk_super_set_parent
ffff8000809b59d8 t clk_super_restore_context
ffff8000809b5a78 t clk_super_mux_restore_context
ffff8000809b5af8 T tegra_clk_register_super_mux
ffff8000809b5c58 T tegra_clk_register_super_clk
ffff8000809b5dc8 T tegra_clk_osc_resume
ffff8000809b5e68 t cclk_super_get_parent
ffff8000809b5ea8 t cclk_super_set_parent
ffff8000809b5ef0 t cclk_super_set_rate
ffff8000809b5f38 t cclk_super_determine_rate
ffff8000809b6098 t cclk_super_recalc_rate
ffff8000809b6150 T tegra_clk_register_super_cclk
ffff8000809b6308 T tegra_cclk_pre_pllx_rate_change
ffff8000809b63d0 T tegra_cclk_post_pllx_rate_change
ffff8000809b6468 t tegra124_dfll_fcpu_remove
ffff8000809b64c8 t tegra124_dfll_fcpu_probe
ffff8000809b6768 t tegra124_disable_cpu_clock
ffff8000809b6788 t tegra124_cpu_clock_resume
ffff8000809b67f0 t tegra124_clk_src_onecell_get
ffff8000809b6858 t tegra124_wait_cpu_in_reset
ffff8000809b68b8 t tegra124_reset_assert
ffff8000809b6908 t tegra124_reset_deassert
ffff8000809b6958 t tegra124_cpu_clock_suspend
ffff8000809b6a28 T tegra_cvb_add_opp_table
ffff8000809b6d28 T tegra_cvb_remove_opp_table
ffff8000809b6dc0 t readl
ffff8000809b6de8 T tegra210_clk_emc_dll_enable
ffff8000809b6e28 T tegra210_clk_emc_dll_update_setting
ffff8000809b6e50 T tegra210_clk_emc_update_setting
ffff8000809b6e78 t tegra210_clk_pll_set_gain
ffff8000809b6ed0 t tegra210_clk_adjust_vco_min
ffff8000809b6f08 t tegra210_disable_cpu_clock
ffff8000809b6f28 t tegra210_cpu_clock_resume
ffff8000809b6f68 t tegra210_pll_fixed_mdiv_cfg
ffff8000809b7168 t pll_qlin_p_to_pdiv
ffff8000809b71e8 t pll_expo_p_to_pdiv
ffff8000809b7288 t tegra210_wait_cpu_in_reset
ffff8000809b72e8 T tegra210_xusb_pll_hw_sequence_start
ffff8000809b7328 T tegra210_sata_pll_hw_sequence_start
ffff8000809b7368 T tegra210_put_utmipll_out_iddq
ffff8000809b73a8 T tegra210_plle_hw_sequence_is_enabled
ffff8000809b73d0 T tegra210_xusb_pll_hw_control_enable
ffff8000809b7418 T tegra210_sata_pll_hw_control_enable
ffff8000809b7458 T tegra210_set_sata_pll_seq_sw
ffff8000809b74a8 T tegra210_put_utmipll_in_iddq
ffff8000809b7528 t tegra210_cpu_clock_suspend
ffff8000809b7580 t _pll_misc_chk_default
ffff8000809b7648 t tegra210_plla_set_defaults
ffff8000809b77a8 t tegra210_clk_suspend
ffff8000809b7848 t tegra210_generic_mbist_war
ffff8000809b7908 t tegra210_pllx_dyn_ramp
ffff8000809b7b70 t tegra210_disp_mbist_war
ffff8000809b7c48 t tegra210_vic_mbist_war
ffff8000809b7d48 t tegra210_venc_mbist_war
ffff8000809b7e68 t tegra210_ape_mbist_war
ffff8000809b7f98 t tegra210_reset_assert
ffff8000809b8010 t tegra210_reset_deassert
ffff8000809b80e8 T tegra210_plle_hw_sequence_start
ffff8000809b8208 t tegra210_pllre_set_defaults
ffff8000809b83c8 t tegra210_plld_set_defaults
ffff8000809b85a8 t tegra210_pllmb_set_defaults
ffff8000809b8710 t tegra210_pllp_set_defaults
ffff8000809b88f0 t tegra210_pllcx_set_defaults
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ffff8000809b8bb0 t _pllc3_set_defaults
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ffff800080aae288 T iommufd_hw_queue_destroy
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ffff800080ab0e68 T iommu_iova_to_phys
ffff800080ab0ef0 T iommu_set_fault_handler
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ffff800080ab17e8 T iommu_replace_device_pasid
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ffff800080ab1bb8 T iommu_fwspec_init
ffff800080ab1e08 T iommu_attach_device_pasid
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ffff800080ab2e18 T iommu_attach_group_handle
ffff800080ab2f48 t __iommu_take_dma_ownership
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ffff800080ab3910 T iommu_unmap
ffff800080ab39d0 T iommu_unmap_fast
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ffff800080ab7020 t trace_event_raw_event_iommu_group_event
ffff800080ab71c0 t trace_event_raw_event_iommu_device_event
ffff800080ab7320 t perf_trace_map
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ffff800080ab76f0 t perf_trace_iommu_group_event
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ffff800080abdd70 t arm_mali_lpae_alloc_pgtable
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ffff800080abedd8 t arm_lpae_map_pages
ffff800080abf0e8 T init_iova_domain
ffff800080abf190 t private_find_iova
ffff800080abf1e8 T find_iova
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ffff800080abf348 T reserve_iova
ffff800080abf4b8 T alloc_iova
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ffff800080abf898 T iova_cache_put
ffff800080abf978 T iova_cache_get
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ffff800080ac0028 t free_iova_rcaches
ffff800080ac0188 T put_iova_domain
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ffff800080ac0a08 T of_iommu_get_resv_regions
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ffff800080ac0d90 t of_pci_iommu_init
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ffff800080ac10a0 t readl
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ffff80008106f510 d exynos5250_dp_video_phy
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ffff800081088228 d mt6893_pin_r0_range
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ffff800081089c98 d mt6893_pin_ies_range
ffff80008108a5d0 d mt6893_pin_smt_range
ffff80008108ac38 d mt6893_pin_do_range
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ffff80008108ee28 d mt7981_pin_pu_range
ffff80008108ef80 d mt7981_pin_smt_range
ffff80008108f3f8 d mt7981_pin_ies_range
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ffff80008108f888 d mt7981_pin_di_range
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ffff80008108f8d0 d mt7986b_pinctrl_of_match
ffff80008108fa60 d mt7986a_pinctrl_of_match
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ffff800081093c68 d mt7988_pcie_groups
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ffff800081093df0 d mt7988_dfd_groups
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ffff800081093e68 d mt7988_int_usxgmii_groups
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ffff800081094df0 d mt7988_2p5gbe_led0_pins
ffff800081094df8 d mt7988_gbe3_led0_pins
ffff800081094e00 d mt7988_gbe2_led0_pins
ffff800081094e08 d mt7988_gbe1_led0_pins
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ffff800081094e18 d mt7988_2p5gbe_led1_pins
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ffff800081094e28 d mt7988_gbe2_led1_pins
ffff800081094e30 d mt7988_gbe1_led1_pins
ffff800081094e38 d mt7988_gbe0_led1_pins
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ffff800081094e80 d mt7988_net_wo2_uart_txd_1_pins
ffff800081094e88 d mt7988_net_wo1_uart_txd_1_pins
ffff800081094e90 d mt7988_net_wo0_uart_txd_1_pins
ffff800081094e98 d mt7988_tops_uart1_2_pins
ffff800081094ea0 d mt7988_uart1_2_lite_pins
ffff800081094ea8 d mt7988_uart1_2_pins
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ffff800081094ee8 d mt7988_tops_uart0_2_pins
ffff800081094ef0 d mt7988_uart0_pins
ffff800081094ef8 d mt7988_tops_uart1_1_pins
ffff800081094f00 d mt7988_tops_uart0_1_pins
ffff800081094f08 d mt7988_tops_uart1_0_pins
ffff800081094f10 d mt7988_net_wo2_uart_txd_0_pins
ffff800081094f18 d mt7988_net_wo1_uart_txd_0_pins
ffff800081094f20 d mt7988_net_wo0_uart_txd_0_pins
ffff800081094f28 d mt7988_uart2_1_pins
ffff800081094f38 d mt7988_uart1_0_pins
ffff800081094f48 d mt7988_uart2_0_pins
ffff800081094f58 d mt7988_tops_uart0_0_pins
ffff800081094f60 d mt7988_uart2_pins
ffff800081094f70 d mt7988_emmc_51_pins
ffff800081094fa0 d mt7988_sdcard_pins
ffff800081094fb8 d mt7988_emmc_45_pins
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ffff800081095000 d mt7988_spi2_wp_hold_pins
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ffff800081095018 d mt7988_spi1_pins
ffff800081095028 d mt7988_spi0_pins
ffff800081095038 d mt7988_spi0_wp_hold_pins
ffff800081095040 d mt7988_watchdog_pins
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ffff800081095060 d mt7988_pcie_wake_n2_0_pins
ffff800081095068 d mt7988_pcie_clk_req_n1_pins
ffff800081095070 d mt7988_pcie_wake_n1_0_pins
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ffff800081095080 d mt7988_pcie_2l_1_pereset_pins
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ffff800081095090 d mt7988_pcie_1l_1_pereset_pins
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ffff8000810950b8 d mt7988_pcie_p2_phy_i2c_pins
ffff8000810950c0 d mt7988_pcie_p3_phy_i2c_pins
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ffff8000810950d0 d mt7988_pcie_p0_phy_i2c_pins
ffff8000810950d8 d mt7988_pcie_clk_req_n0_1_pins
ffff8000810950e0 d mt7988_pcie_clk_req_n3_pins
ffff8000810950e8 d mt7988_pcie_wake_n3_0_pins
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ffff800081095130 d mt7988_i2c1_2_pins
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ffff800081095158 d mt7988_u30_phy_i2c1_pins
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ffff8000810e1760 d tdmb_sclk_slv_pins
ffff8000810e1768 d tdmb_sclk_pins
ffff8000810e1770 d tdmc_dout3_pins
ffff8000810e1778 d tdmc_din3_pins
ffff8000810e1780 d tdmc_dout2_pins
ffff8000810e1788 d tdmc_din2_pins
ffff8000810e1790 d tdmc_dout1_pins
ffff8000810e1798 d tdmc_din1_pins
ffff8000810e17a0 d tdmc_dout0_pins
ffff8000810e17a8 d tdmc_din0_pins
ffff8000810e17b0 d tdmc_fs_slv_pins
ffff8000810e17b8 d tdmc_fs_pins
ffff8000810e17c0 d tdmc_sclk_slv_pins
ffff8000810e17c8 d tdmc_sclk_pins
ffff8000810e17d0 d tdma_din1_pins
ffff8000810e17d8 d tdma_dout1_pins
ffff8000810e17e0 d tdma_dout0_x15_pins
ffff8000810e17e8 d tdma_dout0_x14_pins
ffff8000810e17f0 d tdma_din0_pins
ffff8000810e17f8 d tdma_fs_slv_pins
ffff8000810e1800 d tdma_fs_pins
ffff8000810e1808 d tdma_sclk_slv_pins
ffff8000810e1810 d tdma_sclk_pins
ffff8000810e1818 d mclk_b_pins
ffff8000810e1820 d mclk_c_pins
ffff8000810e1828 d pdm_din3_pins
ffff8000810e1830 d pdm_din2_pins
ffff8000810e1838 d pdm_din1_pins
ffff8000810e1840 d pdm_din0_pins
ffff8000810e1848 d pdm_dclk_a19_pins
ffff8000810e1850 d pdm_dclk_a14_pins
ffff8000810e1858 d eth_txd3_rgmii_pins
ffff8000810e1860 d eth_txd2_rgmii_pins
ffff8000810e1868 d eth_rgmii_tx_clk_pins
ffff8000810e1870 d eth_rxd3_rgmii_pins
ffff8000810e1878 d eth_rxd2_rgmii_pins
ffff8000810e1880 d eth_mdc_y_pins
ffff8000810e1888 d eth_mdio_y_pins
ffff8000810e1890 d eth_rx_dv_y_pins
ffff8000810e1898 d eth_rxd1_y_pins
ffff8000810e18a0 d eth_rxd0_y_pins
ffff8000810e18a8 d eth_rgmii_rx_clk_y_pins
ffff8000810e18b0 d eth_txen_y_pins
ffff8000810e18b8 d eth_txd1_y_pins
ffff8000810e18c0 d eth_txd0_y_pins
ffff8000810e18c8 d eth_mdc_x_pins
ffff8000810e18d0 d eth_mdio_x_pins
ffff8000810e18d8 d eth_rx_dv_x_pins
ffff8000810e18e0 d eth_rxd1_x_pins
ffff8000810e18e8 d eth_rxd0_x_pins
ffff8000810e18f0 d eth_rgmii_rx_clk_x_pins
ffff8000810e18f8 d eth_txen_x_pins
ffff8000810e1900 d eth_txd1_x_pins
ffff8000810e1908 d eth_txd0_x_pins
ffff8000810e1910 d jtag_tms_x_pins
ffff8000810e1918 d jtag_clk_x_pins
ffff8000810e1920 d jtag_tdi_x_pins
ffff8000810e1928 d jtag_tdo_x_pins
ffff8000810e1930 d spdif_out_a20_pins
ffff8000810e1938 d spdif_out_a19_pins
ffff8000810e1940 d spdif_out_a11_pins
ffff8000810e1948 d spdif_out_a1_pins
ffff8000810e1950 d spdif_out_z_pins
ffff8000810e1958 d spdif_in_a20_pins
ffff8000810e1960 d spdif_in_a19_pins
ffff8000810e1968 d spdif_in_a7_pins
ffff8000810e1970 d spdif_in_a1_pins
ffff8000810e1978 d spdif_in_z_pins
ffff8000810e1980 d pwm_vs_pins
ffff8000810e1988 d pwm_d_x16_pins
ffff8000810e1990 d pwm_d_x11_pins
ffff8000810e1998 d pwm_c_a_pins
ffff8000810e19a0 d pwm_c_x17_pins
ffff8000810e19a8 d pwm_c_x10_pins
ffff8000810e19b0 d pwm_b_a_pins
ffff8000810e19b8 d pwm_b_x_pins
ffff8000810e19c0 d pwm_b_z_pins
ffff8000810e19c8 d pwm_a_a_pins
ffff8000810e19d0 d pwm_a_x20_pins
ffff8000810e19d8 d pwm_a_x18_pins
ffff8000810e19e0 d pwm_a_z_pins
ffff8000810e19e8 d uart_ao_rts_b_z_pins
ffff8000810e19f0 d uart_ao_cts_b_z_pins
ffff8000810e19f8 d uart_ao_rx_b_z_pins
ffff8000810e1a00 d uart_ao_tx_b_z_pins
ffff8000810e1a08 d uart_rx_b_x_pins
ffff8000810e1a10 d uart_tx_b_x_pins
ffff8000810e1a18 d uart_cts_b_x_pins
ffff8000810e1a20 d uart_rts_b_x_pins
ffff8000810e1a28 d uart_rx_b_z_pins
ffff8000810e1a30 d uart_tx_b_z_pins
ffff8000810e1a38 d uart_cts_b_z_pins
ffff8000810e1a40 d uart_rts_b_z_pins
ffff8000810e1a48 d uart_rx_a_pins
ffff8000810e1a50 d uart_tx_a_pins
ffff8000810e1a58 d uart_cts_a_pins
ffff8000810e1a60 d uart_rts_a_pins
ffff8000810e1a68 d i2c3_sck_a20_pins
ffff8000810e1a70 d i2c3_sda_a19_pins
ffff8000810e1a78 d i2c3_sck_a13_pins
ffff8000810e1a80 d i2c3_sda_a12_pins
ffff8000810e1a88 d i2c3_sck_a7_pins
ffff8000810e1a90 d i2c3_sda_a6_pins
ffff8000810e1a98 d i2c2_sck_a_pins
ffff8000810e1aa0 d i2c2_sda_a_pins
ffff8000810e1aa8 d i2c2_sda_x_pins
ffff8000810e1ab0 d i2c2_sck_x_pins
ffff8000810e1ab8 d i2c1_sda_x_pins
ffff8000810e1ac0 d i2c1_sck_x_pins
ffff8000810e1ac8 d i2c1_sda_z_pins
ffff8000810e1ad0 d i2c1_sck_z_pins
ffff8000810e1ad8 d i2c0_sda_pins
ffff8000810e1ae0 d i2c0_sck_pins
ffff8000810e1ae8 d spi1_ss1_pins
ffff8000810e1af0 d spi1_ss0_a_pins
ffff8000810e1af8 d spi1_miso_a_pins
ffff8000810e1b00 d spi1_mosi_a_pins
ffff8000810e1b08 d spi1_clk_a_pins
ffff8000810e1b10 d spi1_ss0_x_pins
ffff8000810e1b18 d spi1_miso_x_pins
ffff8000810e1b20 d spi1_mosi_x_pins
ffff8000810e1b28 d spi1_clk_x_pins
ffff8000810e1b30 d spi0_ss2_pins
ffff8000810e1b38 d spi0_ss1_pins
ffff8000810e1b40 d spi0_ss0_pins
ffff8000810e1b48 d spi0_miso_pins
ffff8000810e1b50 d spi0_mosi_pins
ffff8000810e1b58 d spi0_clk_pins
ffff8000810e1b60 d sdio_cmd_pins
ffff8000810e1b68 d sdio_clk_pins
ffff8000810e1b70 d sdio_d3_pins
ffff8000810e1b78 d sdio_d2_pins
ffff8000810e1b80 d sdio_d1_pins
ffff8000810e1b88 d sdio_d0_pins
ffff8000810e1b90 d nor_cs_pins
ffff8000810e1b98 d nor_wp_pins
ffff8000810e1ba0 d nor_c_pins
ffff8000810e1ba8 d nor_q_pins
ffff8000810e1bb0 d nor_d_pins
ffff8000810e1bb8 d nor_hold_pins
ffff8000810e1bc0 d nand_rb0_pins
ffff8000810e1bc8 d nand_ren_wr_pins
ffff8000810e1bd0 d nand_wen_clk_pins
ffff8000810e1bd8 d nand_cle_pins
ffff8000810e1be0 d nand_ale_pins
ffff8000810e1be8 d nand_ce0_pins
ffff8000810e1bf0 d emmc_ds_pins
ffff8000810e1bf8 d emmc_cmd_pins
ffff8000810e1c00 d emmc_clk_pins
ffff8000810e1c08 d emmc_nand_d7_pins
ffff8000810e1c10 d emmc_nand_d6_pins
ffff8000810e1c18 d emmc_nand_d5_pins
ffff8000810e1c20 d emmc_nand_d4_pins
ffff8000810e1c28 d emmc_nand_d3_pins
ffff8000810e1c30 d emmc_nand_d2_pins
ffff8000810e1c38 d emmc_nand_d1_pins
ffff8000810e1c40 d emmc_nand_d0_pins
ffff8000810e1c48 d meson_axg_aobus_pins
ffff8000810e1db0 d meson_axg_periphs_pins
ffff8000810e25c0 d meson_g12a_pinctrl_dt_match
ffff8000810e2818 d meson_g12a_aobus_pinctrl_data
ffff8000810e2870 d meson_g12a_periphs_pinctrl_data
ffff8000810e28c8 d meson_g12a_aobus_pmx_banks_data
ffff8000810e28d8 d meson_g12a_aobus_pmx_banks
ffff8000810e2908 d meson_g12a_periphs_pmx_banks_data
ffff8000810e2918 d meson_g12a_periphs_pmx_banks
ffff8000810e29a8 d meson_g12a_aobus_banks
ffff8000810e2a38 d meson_g12a_periphs_banks
ffff8000810e2be8 d meson_g12a_aobus_functions
ffff8000810e2db0 d meson_g12a_periphs_functions
ffff8000810e3170 d mclk0_ao_groups
ffff8000810e3178 d tdm_ao_b_groups
ffff8000810e31c8 d spdif_ao_out_groups
ffff8000810e31d0 d tsin_ao_a_groups
ffff8000810e31f0 d cec_ao_b_groups
ffff8000810e31f8 d cec_ao_a_groups
ffff8000810e3200 d jtag_a_groups
ffff8000810e3220 d pwm_ao_d_groups
ffff8000810e3238 d pwm_ao_c_groups
ffff8000810e3250 d pwm_ao_b_groups
ffff8000810e3258 d pwm_ao_a_groups
ffff8000810e3268 d pwm_a_e_groups
ffff8000810e3270 d remote_ao_out_groups
ffff8000810e3278 d remote_ao_input_groups
ffff8000810e3280 d i2c_ao_slave_groups
ffff8000810e3290 d i2c_ao_groups
ffff8000810e32b0 d uart_ao_b_groups
ffff8000810e32e0 d uart_ao_a_groups
ffff8000810e3300 d gpio_aobus_groups
ffff8000810e3378 d pcie_clkreqn_groups
ffff8000810e3380 d tdm_c_groups
ffff8000810e3440 d tdm_b_groups
ffff8000810e34b0 d tdm_a_groups
ffff8000810e34f0 d mclk1_groups
ffff8000810e3508 d mclk0_groups
ffff8000810e3510 d spdif_out_groups
ffff8000810e3528 d spdif_in_groups
ffff8000810e3540 d pdm_groups
ffff8000810e35e0 d hdmitx_groups
ffff8000810e35f8 d tsin_b_groups
ffff8000810e3678 d tsin_a_groups
ffff8000810e3698 d bt565_a_groups
ffff8000810e36f0 d jtag_b_groups
ffff8000810e3710 d cec_ao_b_h_groups
ffff8000810e3718 d cec_ao_a_h_groups
ffff8000810e3720 d pwm_f_groups
ffff8000810e3740 d pwm_e_groups
ffff8000810e3748 d pwm_d_groups
ffff8000810e3768 d pwm_c_groups
ffff8000810e3788 d pwm_b_groups
ffff8000810e37b0 d pwm_a_groups
ffff8000810e37b8 d eth_groups
ffff8000810e3838 d iso7816_groups
ffff8000810e3878 d uart_ao_a_c_groups
ffff8000810e3888 d uart_c_groups
ffff8000810e38a8 d uart_b_groups
ffff8000810e38b8 d uart_a_groups
ffff8000810e38d8 d i2c3_groups
ffff8000810e38f8 d i2c2_groups
ffff8000810e3918 d i2c1_groups
ffff8000810e3948 d i2c0_groups
ffff8000810e3978 d spi1_groups
ffff8000810e3998 d spi0_groups
ffff8000810e39d8 d sdcard_groups
ffff8000810e3a38 d sdio_groups
ffff8000810e3a70 d nor_groups
ffff8000810e3aa0 d nand_groups
ffff8000810e3b20 d emmc_groups
ffff8000810e3b78 d gpio_periphs_groups
ffff8000810e3e20 d meson_g12a_aobus_groups
ffff8000810e4640 d __compound_literal.499
ffff8000810e4648 d __compound_literal.498
ffff8000810e4650 d __compound_literal.497
ffff8000810e4658 d __compound_literal.496
ffff8000810e4660 d __compound_literal.495
ffff8000810e4668 d __compound_literal.494
ffff8000810e4670 d __compound_literal.493
ffff8000810e4678 d __compound_literal.492
ffff8000810e4680 d __compound_literal.491
ffff8000810e4688 d __compound_literal.490
ffff8000810e4690 d __compound_literal.489
ffff8000810e4698 d __compound_literal.488
ffff8000810e46a0 d __compound_literal.487
ffff8000810e46a8 d __compound_literal.486
ffff8000810e46b0 d __compound_literal.485
ffff8000810e46b8 d __compound_literal.484
ffff8000810e46c0 d __compound_literal.483
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ffff8000810e46d0 d __compound_literal.481
ffff8000810e46d8 d __compound_literal.480
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ffff8000810e46f0 d __compound_literal.477
ffff8000810e46f8 d __compound_literal.476
ffff8000810e4700 d __compound_literal.475
ffff8000810e4708 d __compound_literal.474
ffff8000810e4710 d __compound_literal.473
ffff8000810e4718 d __compound_literal.472
ffff8000810e4720 d __compound_literal.471
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ffff8000810e4730 d __compound_literal.469
ffff8000810e4738 d __compound_literal.468
ffff8000810e4740 d __compound_literal.467
ffff8000810e4748 d __compound_literal.466
ffff8000810e4750 d __compound_literal.465
ffff8000810e4758 d __compound_literal.464
ffff8000810e4760 d __compound_literal.463
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ffff8000810e4778 d __compound_literal.460
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ffff8000810e47f8 d __compound_literal.444
ffff8000810e4800 d __compound_literal.443
ffff8000810e4808 d __compound_literal.442
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ffff8000810e4818 d __compound_literal.440
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ffff8000810e4828 d __compound_literal.438
ffff8000810e4830 d __compound_literal.437
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ffff8000810e4858 d __compound_literal.432
ffff8000810e4860 d __compound_literal.431
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ffff8000810e4888 d __compound_literal.426
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ffff8000810e4898 d __compound_literal.424
ffff8000810e48a0 d __compound_literal.423
ffff8000810e48a8 d __compound_literal.422
ffff8000810e48b0 d __compound_literal.421
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ffff8000810e48c0 d mclk0_ao_pins
ffff8000810e48c8 d tdm_ao_b_dout2_pins
ffff8000810e48d0 d tdm_ao_b_dout1_pins
ffff8000810e48d8 d tdm_ao_b_dout0_pins
ffff8000810e48e0 d tdm_ao_b_din2_pins
ffff8000810e48e8 d tdm_ao_b_din1_pins
ffff8000810e48f0 d tdm_ao_b_din0_pins
ffff8000810e48f8 d tdm_ao_b_sclk_pins
ffff8000810e4900 d tdm_ao_b_fs_pins
ffff8000810e4908 d tdm_ao_b_slv_sclk_pins
ffff8000810e4910 d tdm_ao_b_slv_fs_pins
ffff8000810e4918 d spdif_ao_out_pins
ffff8000810e4920 d tsin_ao_a_valid_pins
ffff8000810e4928 d tsin_ao_aclk_pins
ffff8000810e4930 d tsin_ao_adin0_pins
ffff8000810e4938 d tsin_ao_asop_pins
ffff8000810e4940 d cec_ao_b_pins
ffff8000810e4948 d cec_ao_a_pins
ffff8000810e4950 d jtag_a_tms_pins
ffff8000810e4958 d jtag_a_clk_pins
ffff8000810e4960 d jtag_a_tdo_pins
ffff8000810e4968 d jtag_a_tdi_pins
ffff8000810e4970 d pwm_ao_d_e_pins
ffff8000810e4978 d pwm_ao_d_10_pins
ffff8000810e4980 d pwm_ao_d_5_pins
ffff8000810e4988 d pwm_ao_c_6_pins
ffff8000810e4990 d pwm_ao_c_hiz_pins
ffff8000810e4998 d pwm_ao_c_4_pins
ffff8000810e49a0 d pwm_ao_b_pins
ffff8000810e49a8 d pwm_ao_a_hiz_pins
ffff8000810e49b0 d pwm_ao_a_pins
ffff8000810e49b8 d pwm_a_e_pins
ffff8000810e49c0 d remote_ao_out_pins
ffff8000810e49c8 d remote_ao_input_pins
ffff8000810e49d0 d i2c_ao_slave_sda_pins
ffff8000810e49d8 d i2c_ao_slave_sck_pins
ffff8000810e49e0 d i2c_ao_sda_e_pins
ffff8000810e49e8 d i2c_ao_sck_e_pins
ffff8000810e49f0 d i2c_ao_sda_pins
ffff8000810e49f8 d i2c_ao_sck_pins
ffff8000810e4a00 d uart_ao_b_rts_pins
ffff8000810e4a08 d uart_ao_b_cts_pins
ffff8000810e4a10 d uart_ao_b_rx_9_pins
ffff8000810e4a18 d uart_ao_b_tx_8_pins
ffff8000810e4a20 d uart_ao_b_rx_3_pins
ffff8000810e4a28 d uart_ao_b_tx_2_pins
ffff8000810e4a30 d uart_ao_a_rts_pins
ffff8000810e4a38 d uart_ao_a_cts_pins
ffff8000810e4a40 d uart_ao_a_rx_pins
ffff8000810e4a48 d uart_ao_a_tx_pins
ffff8000810e4a50 d meson_g12a_periphs_groups
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ffff8000810e7438 d __compound_literal.418
ffff8000810e7440 d __compound_literal.417
ffff8000810e7448 d __compound_literal.416
ffff8000810e7450 d __compound_literal.415
ffff8000810e7458 d __compound_literal.414
ffff8000810e7460 d __compound_literal.413
ffff8000810e7468 d __compound_literal.412
ffff8000810e7470 d __compound_literal.411
ffff8000810e7478 d __compound_literal.410
ffff8000810e7480 d __compound_literal.409
ffff8000810e7488 d __compound_literal.408
ffff8000810e7490 d __compound_literal.407
ffff8000810e7498 d __compound_literal.406
ffff8000810e74a0 d __compound_literal.405
ffff8000810e74a8 d __compound_literal.404
ffff8000810e74b0 d __compound_literal.403
ffff8000810e74b8 d __compound_literal.402
ffff8000810e74c0 d __compound_literal.401
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ffff8000810e74d8 d __compound_literal.398
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ffff8000810e74f0 d __compound_literal.395
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ffff8000810e7500 d __compound_literal.393
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ffff8000810e8700 d i2c1_sck_h3_pins
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ffff8000810e8720 d i2c0_sck_z8_pins
ffff8000810e8728 d i2c0_sda_z7_pins
ffff8000810e8730 d i2c0_sck_z1_pins
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ffff8000810e8770 d spi0_clk_x_pins
ffff8000810e8778 d spi0_ss0_x_pins
ffff8000810e8780 d spi0_miso_x_pins
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ffff8000810e8798 d spi0_ss0_c_pins
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ffff8000810e87a8 d spi0_mosi_c_pins
ffff8000810e87b0 d sdcard_cmd_z_pins
ffff8000810e87b8 d sdcard_clk_z_pins
ffff8000810e87c0 d sdcard_d3_z_pins
ffff8000810e87c8 d sdcard_d2_z_pins
ffff8000810e87d0 d sdcard_d1_z_pins
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ffff8000810e87f8 d sdcard_d2_c_pins
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ffff8000810e8880 d nand_ren_wr_pins
ffff8000810e8888 d nand_ce0_pins
ffff8000810e8890 d nand_cle_pins
ffff8000810e8898 d nand_ale_pins
ffff8000810e88a0 d nand_wen_clk_pins
ffff8000810e88a8 d emmc_nand_ds_pins
ffff8000810e88b0 d emmc_cmd_pins
ffff8000810e88b8 d emmc_clk_pins
ffff8000810e88c0 d emmc_nand_d7_pins
ffff8000810e88c8 d emmc_nand_d6_pins
ffff8000810e88d0 d emmc_nand_d5_pins
ffff8000810e88d8 d emmc_nand_d4_pins
ffff8000810e88e0 d emmc_nand_d3_pins
ffff8000810e88e8 d emmc_nand_d2_pins
ffff8000810e88f0 d emmc_nand_d1_pins
ffff8000810e88f8 d emmc_nand_d0_pins
ffff8000810e8900 d meson_g12a_aobus_pins
ffff8000810e8a68 d meson_g12a_periphs_pins
ffff8000810e9260 d meson_a1_pinctrl_dt_match
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ffff8000810e9448 d meson_a1_periphs_pmx_banks_data
ffff8000810e9458 d meson_a1_periphs_pmx_banks
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ffff8000810e9a90 d tdm_b_groups
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ffff8000810e9b08 d cec_b_groups
ffff8000810e9b10 d cec_a_groups
ffff8000810e9b18 d clk25_groups
ffff8000810e9b20 d sw_groups
ffff8000810e9b30 d spdif_in_groups
ffff8000810e9b40 d remote_out_groups
ffff8000810e9b48 d clk_32k_in_groups
ffff8000810e9b50 d jtag_a_groups
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ffff8000810e9c60 d i2c2_groups
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ffff8000810e9e28 d pwm_b_hiz_groups
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ffff8000810ecaf0 d gen_clk_f8_pins
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ffff8000810ecb10 d pdm_din1_a_pins
ffff8000810ecb18 d pdm_din2_a_pins
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ffff8000810ecb28 d pdm_din2_x_pins
ffff8000810ecb30 d pdm_din1_x_pins
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ffff8000810ecb50 d spi_a_miso_a_pins
ffff8000810ecb58 d spi_a_mosi_a_pins
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ffff8000810ecb68 d spi_a_ss0_x9_pins
ffff8000810ecb70 d spi_a_miso_x8_pins
ffff8000810ecb78 d spi_a_mosi_x7_pins
ffff8000810ecb80 d spi_a_miso_x5_pins
ffff8000810ecb88 d spi_a_sclk_x4_pins
ffff8000810ecb90 d spi_a_ss0_x3_pins
ffff8000810ecb98 d spi_a_mosi_x2_pins
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ffff8000810ecbb8 d tdm_a_din1_pins
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ffff8000810ecc40 d pwm_e_x14_pins
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ffff8000810ecce0 d uart_c_tx_x15_pins
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ffff8000810ecd58 d i2c_slave_sda_a_pins
ffff8000810ecd60 d i2c_slave_sck_a_pins
ffff8000810ecd68 d i2c3_sda_x_pins
ffff8000810ecd70 d i2c3_sck_x_pins
ffff8000810ecd78 d i2c3_sda_f_pins
ffff8000810ecd80 d i2c3_sck_f_pins
ffff8000810ecd88 d i2c2_sda_a9_pins
ffff8000810ecd90 d i2c2_sck_a8_pins
ffff8000810ecd98 d i2c2_sda_a5_pins
ffff8000810ecda0 d i2c2_sck_a4_pins
ffff8000810ecda8 d i2c2_sda_x16_pins
ffff8000810ecdb0 d i2c2_sck_x15_pins
ffff8000810ecdb8 d i2c2_sda_x1_pins
ffff8000810ecdc0 d i2c2_sck_x0_pins
ffff8000810ecdc8 d i2c1_sck_a_pins
ffff8000810ecdd0 d i2c1_sda_a_pins
ffff8000810ecdd8 d i2c1_sck_x_pins
ffff8000810ecde0 d i2c1_sda_x_pins
ffff8000810ecde8 d i2c0_sda_f12_pins
ffff8000810ecdf0 d i2c0_sck_f11_pins
ffff8000810ecdf8 d i2c0_sda_f10_pins
ffff8000810ece00 d i2c0_sck_f9_pins
ffff8000810ece08 d spif_cs_pins
ffff8000810ece10 d spif_clk_pins
ffff8000810ece18 d spif_hold_n_pins
ffff8000810ece20 d spif_wp_n_pins
ffff8000810ece28 d spif_mi_pins
ffff8000810ece30 d spif_mo_pins
ffff8000810ece38 d sdcard_cmd_x_pins
ffff8000810ece40 d sdcard_clk_x_pins
ffff8000810ece48 d sdcard_d3_x_pins
ffff8000810ece50 d sdcard_d2_x_pins
ffff8000810ece58 d sdcard_d1_x_pins
ffff8000810ece60 d sdcard_d0_x_pins
ffff8000810ece68 d sdcard_cmd_b_pins
ffff8000810ece70 d sdcard_clk_b_pins
ffff8000810ece78 d sdcard_d3_b_pins
ffff8000810ece80 d sdcard_d2_b_pins
ffff8000810ece88 d sdcard_d1_b_pins
ffff8000810ece90 d sdcard_d0_b_pins
ffff8000810ece98 d psram_dqs_dm_pins
ffff8000810ecea0 d psram_adq7_pins
ffff8000810ecea8 d psram_adq6_pins
ffff8000810eceb0 d psram_adq5_pins
ffff8000810eceb8 d psram_adq4_pins
ffff8000810ecec0 d psram_adq3_pins
ffff8000810ecec8 d psram_adq2_pins
ffff8000810eced0 d psram_adq1_pins
ffff8000810eced8 d psram_adq0_pins
ffff8000810ecee0 d psram_rst_n_pins
ffff8000810ecee8 d psram_ce_n_pins
ffff8000810ecef0 d psram_clkp_pins
ffff8000810ecef8 d psram_clkn_pins
ffff8000810ecf00 d meson_a1_periphs_pins
ffff8000810ed4d0 d meson_s4_pinctrl_dt_match
ffff8000810ed660 d meson_s4_periphs_pinctrl_data
ffff8000810ed6b8 d meson_s4_periphs_pmx_banks_data
ffff8000810ed6c8 d meson_s4_periphs_pmx_banks
ffff8000810ed788 d meson_s4_periphs_banks
ffff8000810ed9c8 d meson_s4_periphs_functions
ffff8000810edf20 d s2_demod_groups
ffff8000810edf60 d diseqc_out_groups
ffff8000810edf68 d tsin_b1_groups
ffff8000810edf88 d tsin_b_groups
ffff8000810edfc8 d tsin_a_groups
ffff8000810edfe8 d dtv_groups
ffff8000810ee010 d i2c_slave_groups
ffff8000810ee020 d sdio_groups
ffff8000810ee050 d gen_clk_groups
ffff8000810ee068 d spi_a_groups
ffff8000810ee0d8 d eth_groups
ffff8000810ee0e8 d spdif_in_groups
ffff8000810ee0f0 d spdif_out_groups
ffff8000810ee100 d ao_cec_b_groups
ffff8000810ee108 d ao_cec_a_groups
ffff8000810ee110 d hdmitx_groups
ffff8000810ee128 d mic_mute_groups
ffff8000810ee138 d pwm_j_groups
ffff8000810ee140 d pwm_i_groups
ffff8000810ee150 d pwm_h_groups
ffff8000810ee158 d pwm_g_groups
ffff8000810ee168 d pwm_f_groups
ffff8000810ee178 d pwm_e_groups
ffff8000810ee188 d pwm_d_groups
ffff8000810ee198 d pwm_c_groups
ffff8000810ee1a8 d pwm_b_groups
ffff8000810ee1b8 d pwm_a_groups
ffff8000810ee1c0 d pwm_g_hiz_groups
ffff8000810ee1c8 d pwm_c_hiz_groups
ffff8000810ee1d0 d pwm_b_hiz_groups
ffff8000810ee1d8 d pwm_a_hiz_groups
ffff8000810ee1e0 d clk_32k_in_groups
ffff8000810ee1e8 d clk12_24_groups
ffff8000810ee1f0 d remote_in_groups
ffff8000810ee1f8 d remote_out_groups
ffff8000810ee200 d mclk_2_groups
ffff8000810ee208 d mclk_1_groups
ffff8000810ee228 d tdm_groups
ffff8000810ee2f8 d iso7816_groups
ffff8000810ee318 d pdm_groups
ffff8000810ee390 d jtag_2_groups
ffff8000810ee3b0 d jtag_1_groups
ffff8000810ee3d0 d sdcard_groups
ffff8000810ee438 d spif_groups
ffff8000810ee468 d nand_groups
ffff8000810ee4d0 d emmc_groups
ffff8000810ee530 d uart_e_groups
ffff8000810ee560 d uart_d_groups
ffff8000810ee5a0 d uart_c_groups
ffff8000810ee5b0 d uart_b_groups
ffff8000810ee5f0 d uart_a_groups
ffff8000810ee610 d i2c4_groups
ffff8000810ee640 d i2c3_groups
ffff8000810ee660 d i2c2_groups
ffff8000810ee690 d i2c1_groups
ffff8000810ee6d0 d i2c0_groups
ffff8000810ee6e0 d gpio_periphs_groups
ffff8000810ee970 d meson_s4_periphs_groups
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ffff8000810f11e0 d __compound_literal.402
ffff8000810f11e8 d __compound_literal.401
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ffff8000810f1200 d __compound_literal.398
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ffff8000810f1990 d __compound_literal.156
ffff8000810f1998 d __compound_literal.155
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ffff8000810f1e80 d gen_clk_z9_pins
ffff8000810f1e88 d s2_demod_gpio0_pins
ffff8000810f1e90 d s2_demod_gpio1_pins
ffff8000810f1e98 d diseqc_out_pins
ffff8000810f1ea0 d s2_demod_gpio2_pins
ffff8000810f1ea8 d s2_demod_gpio3_pins
ffff8000810f1eb0 d s2_demod_gpio4_pins
ffff8000810f1eb8 d s2_demod_gpio5_pins
ffff8000810f1ec0 d s2_demod_gpio6_pins
ffff8000810f1ec8 d s2_demod_gpio7_pins
ffff8000810f1ed0 d tsin_b_d0_z_pins
ffff8000810f1ed8 d tsin_b_valid_z_pins
ffff8000810f1ee0 d tsin_b_sop_z_pins
ffff8000810f1ee8 d tsin_b_clk_z_pins
ffff8000810f1ef0 d pwm_e_z_pins
ffff8000810f1ef8 d pwm_f_z_pins
ffff8000810f1f00 d pwm_g_z_pins
ffff8000810f1f08 d uart_d_rts_z_pins
ffff8000810f1f10 d uart_d_cts_z_pins
ffff8000810f1f18 d uart_d_rx_z_pins
ffff8000810f1f20 d uart_d_tx_z_pins
ffff8000810f1f28 d i2c4_sda_z_pins
ffff8000810f1f30 d i2c4_scl_z_pins
ffff8000810f1f38 d spi_a_ss2_z_pins
ffff8000810f1f40 d spi_a_ss1_z_pins
ffff8000810f1f48 d spi_a_ss0_z_pins
ffff8000810f1f50 d spi_a_clk_z_pins
ffff8000810f1f58 d spi_a_mosi_z_pins
ffff8000810f1f60 d spi_a_miso_z_pins
ffff8000810f1f68 d pdm_dclk_z_pins
ffff8000810f1f70 d pdm_din0_z_pins
ffff8000810f1f78 d pdm_din1_z_pins
ffff8000810f1f80 d uart_e_rx_z9_pins
ffff8000810f1f88 d uart_e_tx_z8_pins
ffff8000810f1f90 d sdcard_cmd_z_pins
ffff8000810f1f98 d sdcard_clk_z_pins
ffff8000810f1fa0 d sdcard_d3_z_pins
ffff8000810f1fa8 d sdcard_d2_z_pins
ffff8000810f1fb0 d sdcard_d1_z_pins
ffff8000810f1fb8 d sdcard_d0_z_pins
ffff8000810f1fc0 d dtv_b_rf_agc_pins
ffff8000810f1fc8 d dtv_a_rf_agc_pins
ffff8000810f1fd0 d i2c3_scl_z_pins
ffff8000810f1fd8 d i2c3_sda_z_pins
ffff8000810f1fe0 d dtv_b_if_agc_pins
ffff8000810f1fe8 d dtv_a_if_agc_z6_pins
ffff8000810f1ff0 d tsin_a_din0_pins
ffff8000810f1ff8 d tsin_a_valid_pins
ffff8000810f2000 d tsin_a_sop_pins
ffff8000810f2008 d tsin_a_clk_pins
ffff8000810f2010 d uart_e_rx_z12_pins
ffff8000810f2018 d uart_e_tx_z11_pins
ffff8000810f2020 d dtv_a_if_agc_z10_pins
ffff8000810f2028 d spdif_out_z_pins
ffff8000810f2030 d mclk_2_pins
ffff8000810f2038 d tdm_d7_pins
ffff8000810f2040 d tdm_d6_pins
ffff8000810f2048 d tdm_d5_z_pins
ffff8000810f2050 d tdm_d4_z_pins
ffff8000810f2058 d tdm_sclk2_pins
ffff8000810f2060 d tdm_fs2_pins
ffff8000810f2068 d i2c3_scl_x_pins
ffff8000810f2070 d i2c3_sda_x_pins
ffff8000810f2078 d i2c_slave_sda_pins
ffff8000810f2080 d i2c_slave_scl_pins
ffff8000810f2088 d pwm_c_x_pins
ffff8000810f2090 d spi_a_clk_x_pins
ffff8000810f2098 d spi_a_ss0_x_pins
ffff8000810f20a0 d spi_a_miso_x_pins
ffff8000810f20a8 d spi_a_mosi_x_pins
ffff8000810f20b0 d pdm_dclk_x_pins
ffff8000810f20b8 d pdm_din1_x_pins
ffff8000810f20c0 d pdm_din0_x_pins
ffff8000810f20c8 d pwm_b_x_pins
ffff8000810f20d0 d i2c1_scl_x_pins
ffff8000810f20d8 d i2c1_sda_x_pins
ffff8000810f20e0 d pwm_e_x_pins
ffff8000810f20e8 d uart_a_rts_pins
ffff8000810f20f0 d uart_a_cts_pins
ffff8000810f20f8 d uart_a_rx_pins
ffff8000810f2100 d uart_a_tx_pins
ffff8000810f2108 d tdm_sclk0_pins
ffff8000810f2110 d tdm_fs0_pins
ffff8000810f2118 d tdm_d0_pins
ffff8000810f2120 d tdm_d1_pins
ffff8000810f2128 d pwm_f_x_pins
ffff8000810f2130 d pwm_a_x_pins
ffff8000810f2138 d sdio_cmd_pins
ffff8000810f2140 d sdio_clk_pins
ffff8000810f2148 d sdio_d3_pins
ffff8000810f2150 d sdio_d2_pins
ffff8000810f2158 d sdio_d1_pins
ffff8000810f2160 d sdio_d0_pins
ffff8000810f2168 d tsin_b1_d0_pins
ffff8000810f2170 d tsin_b1_valid_pins
ffff8000810f2178 d tsin_b1_sop_pins
ffff8000810f2180 d tsin_b1_clk_pins
ffff8000810f2188 d gen_clk_h_pins
ffff8000810f2190 d spi_a_ss0_h_pins
ffff8000810f2198 d spi_a_clk_h_pins
ffff8000810f21a0 d spi_a_mosi_h_pins
ffff8000810f21a8 d spi_a_miso_h_pins
ffff8000810f21b0 d tdm_d4_h_pins
ffff8000810f21b8 d tdm_d3_h_pins
ffff8000810f21c0 d tdm_d2_h_pins
ffff8000810f21c8 d tdm_fs1_h_pins
ffff8000810f21d0 d tdm_sclk1_h_pins
ffff8000810f21d8 d mclk_1_h_pins
ffff8000810f21e0 d pdm_din1_h_pins
ffff8000810f21e8 d pdm_din0_h_pins
ffff8000810f21f0 d pdm_dclk_h_pins
ffff8000810f21f8 d pwm_i_h_pins
ffff8000810f2200 d pwm_d_h_pins
ffff8000810f2208 d uart_e_rx_h_pins
ffff8000810f2210 d uart_e_tx_h_pins
ffff8000810f2218 d iso7816_data_h_pins
ffff8000810f2220 d iso7816_clk_h_pins
ffff8000810f2228 d uart_d_rts_h_pins
ffff8000810f2230 d uart_d_cts_h_pins
ffff8000810f2238 d uart_d_rx_h_pins
ffff8000810f2240 d uart_d_tx_h_pins
ffff8000810f2248 d ao_cec_b_pins
ffff8000810f2250 d i2c2_scl_h1_pins
ffff8000810f2258 d i2c2_sda_h0_pins
ffff8000810f2260 d eth_act_led_pins
ffff8000810f2268 d eth_link_led_pins
ffff8000810f2270 d i2c2_scl_h9_pins
ffff8000810f2278 d i2c2_sda_h8_pins
ffff8000810f2280 d i2c1_scl_h_pins
ffff8000810f2288 d i2c1_sda_h_pins
ffff8000810f2290 d spdif_in_pins
ffff8000810f2298 d spdif_out_h_pins
ffff8000810f22a0 d ao_cec_a_pins
ffff8000810f22a8 d hdmitx_hpd_in_pins
ffff8000810f22b0 d hdmitx_sck_pins
ffff8000810f22b8 d hdmitx_sda_pins
ffff8000810f22c0 d tsin_b_d0_c_pins
ffff8000810f22c8 d tsin_b_valid_c_pins
ffff8000810f22d0 d tsin_b_sop_c_pins
ffff8000810f22d8 d tsin_b_clk_c_pins
ffff8000810f22e0 d gen_clk_d_pins
ffff8000810f22e8 d i2c2_scl_d_pins
ffff8000810f22f0 d i2c2_sda_d_pins
ffff8000810f22f8 d i2c1_scl_d_pins
ffff8000810f2300 d i2c1_sda_d_pins
ffff8000810f2308 d mic_mute_key_pins
ffff8000810f2310 d mic_mute_en_pins
ffff8000810f2318 d pdm_din1_d_pins
ffff8000810f2320 d pdm_din0_d_pins
ffff8000810f2328 d pdm_dclk_d_pins
ffff8000810f2330 d pwm_c_hiz_pins
ffff8000810f2338 d pwm_a_hiz_pins
ffff8000810f2340 d pwm_b_hiz_pins
ffff8000810f2348 d clk_32k_in_pins
ffff8000810f2350 d pwm_i_d_pins
ffff8000810f2358 d pwm_d_d_pins
ffff8000810f2360 d pwm_c_d_pins
ffff8000810f2368 d pwm_a_d_pins
ffff8000810f2370 d pwm_b_d_pins
ffff8000810f2378 d uart_c_rx_pins
ffff8000810f2380 d uart_c_tx_pins
ffff8000810f2388 d pwm_g_d_pins
ffff8000810f2390 d tdm_d2_d_pins
ffff8000810f2398 d tdm_d3_d_pins
ffff8000810f23a0 d tdm_d4_d_pins
ffff8000810f23a8 d tdm_fs1_d_pins
ffff8000810f23b0 d tdm_sclk1_d_pins
ffff8000810f23b8 d mclk_1_d_pins
ffff8000810f23c0 d i2c4_scl_d_pins
ffff8000810f23c8 d i2c4_sda_d_pins
ffff8000810f23d0 d pwm_g_hiz_pins
ffff8000810f23d8 d clk12_24_pins
ffff8000810f23e0 d jtag_1_tdo_pins
ffff8000810f23e8 d jtag_1_tdi_pins
ffff8000810f23f0 d jtag_1_tms_pins
ffff8000810f23f8 d jtag_1_clk_pins
ffff8000810f2400 d remote_in_pins
ffff8000810f2408 d remote_out_pins
ffff8000810f2410 d uart_b_rts_d_pins
ffff8000810f2418 d uart_b_cts_d_pins
ffff8000810f2420 d uart_b_rx_d_pins
ffff8000810f2428 d uart_b_tx_d_pins
ffff8000810f2430 d tdm_d5_c_pins
ffff8000810f2438 d tdm_d4_c_pins
ffff8000810f2440 d mclk_1_c_pins
ffff8000810f2448 d tdm_sclk1_c_pins
ffff8000810f2450 d tdm_fs1_c_pins
ffff8000810f2458 d tdm_d3_c_pins
ffff8000810f2460 d tdm_d2_c_pins
ffff8000810f2468 d iso7816_data_c_pins
ffff8000810f2470 d iso7816_clk_c_pins
ffff8000810f2478 d pdm_dclk_c_pins
ffff8000810f2480 d i2c4_scl_c_pins
ffff8000810f2488 d i2c4_sda_c_pins
ffff8000810f2490 d pdm_din0_c_pins
ffff8000810f2498 d pdm_din1_c_pins
ffff8000810f24a0 d i2c1_scl_c_pins
ffff8000810f24a8 d i2c1_sda_c_pins
ffff8000810f24b0 d jtag_2_tms_pins
ffff8000810f24b8 d jtag_2_clk_pins
ffff8000810f24c0 d uart_b_tx_c_pins
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ffff8000810f7618 d uart_e_tx_a_pins
ffff8000810f7620 d uart_f_rx_a_pins
ffff8000810f7628 d uart_f_tx_a_pins
ffff8000810f7630 d lcd_clk_a_pins
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ffff8000810f7640 d jtag_a_tdi_pins
ffff8000810f7648 d jtag_a_tms_pins
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ffff8000810f7658 d pdm_din0_a_pins
ffff8000810f7660 d pdm_dclk_z_pins
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ffff8000810f7670 d pwm_c_hiz_pins
ffff8000810f7678 d i2c1_scl_a_pins
ffff8000810f7680 d i2c1_sda_a_pins
ffff8000810f7688 d pwm_l_a_pins
ffff8000810f7690 d pwm_c_pins
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ffff8000810f76a0 d uart_b_tx_a_pins
ffff8000810f76a8 d uart_c_rx_d_pins
ffff8000810f76b0 d uart_c_tx_d_pins
ffff8000810f76b8 d uart_d_rx_d_pins
ffff8000810f76c0 d uart_d_tx_d_pins
ffff8000810f76c8 d tdm_d0_d_pins
ffff8000810f76d0 d tdm_d1_d_pins
ffff8000810f76d8 d mclk_0_d_pins
ffff8000810f76e0 d tdm_sclk0_d_pins
ffff8000810f76e8 d tdm_fs0_d_pins
ffff8000810f76f0 d i2c3_scl_d_pins
ffff8000810f76f8 d i2c3_sda_d_pins
ffff8000810f7700 d pwm_j_d_pins
ffff8000810f7708 d pwm_i_d_pins
ffff8000810f7710 d ir_out_pins
ffff8000810f7718 d ir_in_d0_pins
ffff8000810f7720 d ir_in_d6_pins
ffff8000810f7728 d pdm_din0_d_pins
ffff8000810f7730 d pdm_dclk_d_pins
ffff8000810f7738 d i2c1_scl_d_pins
ffff8000810f7740 d i2c1_sda_d_pins
ffff8000810f7748 d i2c0_scl_d_pins
ffff8000810f7750 d i2c0_sda_d_pins
ffff8000810f7758 d spi_b_ss1_d_pins
ffff8000810f7760 d spi_b_ss0_d_pins
ffff8000810f7768 d spi_b_mosi_d_pins
ffff8000810f7770 d spi_b_clk_d_pins
ffff8000810f7778 d spi_b_miso_d_pins
ffff8000810f7780 d uart_a_rx_d_pins
ffff8000810f7788 d uart_a_tx_d_pins
ffff8000810f7790 d pwm_k_d_pins
ffff8000810f7798 d pwm_f_pins
ffff8000810f77a0 d pwm_d_pins
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ffff8000810f77b0 d eth_led_act_pins
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ffff8000810f77c0 d pwm_g_d_pins
ffff8000810f77c8 d uart_d_rx_x_pins
ffff8000810f77d0 d uart_d_tx_x_pins
ffff8000810f77d8 d i2c1_scl_x_pins
ffff8000810f77e0 d i2c1_sda_x_pins
ffff8000810f77e8 d i2c3_scl_x_pins
ffff8000810f77f0 d i2c3_sda_x_pins
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ffff8000810f7800 d uart_c_rx_x_pins
ffff8000810f7808 d uart_a_tx_x_pins
ffff8000810f7810 d uart_a_rx_x_pins
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ffff8000810f7820 d pwm_i_x10_pins
ffff8000810f7828 d pwm_h_x9_pins
ffff8000810f7830 d pwm_g_x8_pins
ffff8000810f7838 d pwm_n_x_pins
ffff8000810f7840 d pwm_m_x_pins
ffff8000810f7848 d pwm_l_x_pins
ffff8000810f7850 d pwm_k_x4_pins
ffff8000810f7858 d pwm_j_x3_pins
ffff8000810f7860 d pwm_i_x2_pins
ffff8000810f7868 d pwm_h_x1_pins
ffff8000810f7870 d pwm_g_x0_pins
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ffff8000810f7888 d lcd_d16_pins
ffff8000810f7890 d lcd_den_pins
ffff8000810f7898 d lcd_hs_pins
ffff8000810f78a0 d lcd_vs_pins
ffff8000810f78a8 d lcd_d15_pins
ffff8000810f78b0 d lcd_d14_pins
ffff8000810f78b8 d lcd_d13_pins
ffff8000810f78c0 d lcd_d12_pins
ffff8000810f78c8 d lcd_d11_pins
ffff8000810f78d0 d lcd_d10_pins
ffff8000810f78d8 d lcd_d9_pins
ffff8000810f78e0 d lcd_d8_pins
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ffff8000810f78f0 d pdm_dclk_x10_pins
ffff8000810f78f8 d pdm_din0_x9_pins
ffff8000810f7900 d pdm_din0_x6_pins
ffff8000810f7908 d pdm_dclk_x5_pins
ffff8000810f7910 d tdm_fs0_x_pins
ffff8000810f7918 d tdm_sclk0_x_pins
ffff8000810f7920 d mclk_0_x_pins
ffff8000810f7928 d tdm_d0_x_pins
ffff8000810f7930 d tdm_d1_x_pins
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ffff8000810f7940 d spi_b_ss2_x12_pins
ffff8000810f7948 d spi_b_ss1_x_pins
ffff8000810f7950 d spi_b_ss0_x_pins
ffff8000810f7958 d spi_b_mosi_x_pins
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ffff8000810f7968 d spi_b_miso_x_pins
ffff8000810f7970 d spi_b_ss2_x6_pins
ffff8000810f7978 d spi_a_ss2_x_pins
ffff8000810f7980 d spi_a_ss1_x_pins
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ffff8000810f7998 d spi_a_miso_x_pins
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ffff8000810f7a00 d sdio_d2_pins
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ffff8000810f7a20 d i2c3_scl_c_pins
ffff8000810f7a28 d i2c3_sda_c_pins
ffff8000810f7a30 d uart_c_tx_c_pins
ffff8000810f7a38 d uart_c_rx_c_pins
ffff8000810f7a40 d uart_a_tx_c_pins
ffff8000810f7a48 d uart_a_rx_c_pins
ffff8000810f7a50 d pwm_m_c_pins
ffff8000810f7a58 d pwm_l_c_pins
ffff8000810f7a60 d pwm_k_c_pins
ffff8000810f7a68 d pwm_j_c_pins
ffff8000810f7a70 d pwm_i_c_pins
ffff8000810f7a78 d pwm_h_c_pins
ffff8000810f7a80 d pwm_g_c_pins
ffff8000810f7a88 d spi_a_ss1_c_pins
ffff8000810f7a90 d spi_a_ss0_c_pins
ffff8000810f7a98 d spi_a_clk_c_pins
ffff8000810f7aa0 d spi_a_miso_c_pins
ffff8000810f7aa8 d spi_a_mosi_c_pins
ffff8000810f7ab0 d pdm_din0_c_pins
ffff8000810f7ab8 d pdm_dclk_c_pins
ffff8000810f7ac0 d tdm_fs1_pins
ffff8000810f7ac8 d tdm_sclk1_pins
ffff8000810f7ad0 d mclk_1_pins
ffff8000810f7ad8 d tdm_d2_pins
ffff8000810f7ae0 d tdm_d3_pins
ffff8000810f7ae8 d gen_clk_c_pins
ffff8000810f7af0 d jtag_b_tms_pins
ffff8000810f7af8 d jtag_b_clk_pins
ffff8000810f7b00 d uart_b_tx_c_pins
ffff8000810f7b08 d uart_b_rx_c_pins
ffff8000810f7b10 d jtag_b_tdi_pins
ffff8000810f7b18 d jtag_b_tdo_pins
ffff8000810f7b20 d sdcard_cd_pins
ffff8000810f7b28 d sdcard_cmd_pins
ffff8000810f7b30 d sdcard_clk_pins
ffff8000810f7b38 d sdcard_d3_pins
ffff8000810f7b40 d sdcard_d2_pins
ffff8000810f7b48 d sdcard_d1_pins
ffff8000810f7b50 d sdcard_d0_pins
ffff8000810f7b58 d pdm_din0_b_pins
ffff8000810f7b60 d pdm_dclk_b_pins
ffff8000810f7b68 d uart_d_rx_b_pins
ffff8000810f7b70 d uart_d_tx_b_pins
ffff8000810f7b78 d uart_a_rts_b_pins
ffff8000810f7b80 d uart_a_cts_b_pins
ffff8000810f7b88 d uart_a_rx_b_pins
ffff8000810f7b90 d uart_a_tx_b_pins
ffff8000810f7b98 d i2c1_scl_b_pins
ffff8000810f7ba0 d i2c1_sda_b_pins
ffff8000810f7ba8 d spi_a_ss2_b_pins
ffff8000810f7bb0 d spi_a_ss1_b_pins
ffff8000810f7bb8 d spi_a_ss0_b_pins
ffff8000810f7bc0 d spi_a_clk_b_pins
ffff8000810f7bc8 d spi_a_miso_b_pins
ffff8000810f7bd0 d spi_a_mosi_b_pins
ffff8000810f7bd8 d lcd_d7_pins
ffff8000810f7be0 d lcd_d6_pins
ffff8000810f7be8 d lcd_d5_pins
ffff8000810f7bf0 d lcd_d4_pins
ffff8000810f7bf8 d lcd_d3_pins
ffff8000810f7c00 d lcd_d2_pins
ffff8000810f7c08 d lcd_d1_pins
ffff8000810f7c10 d lcd_d0_pins
ffff8000810f7c18 d spif_clk_loop_pins
ffff8000810f7c20 d spif_cs_pins
ffff8000810f7c28 d pwm_n_b_pins
ffff8000810f7c30 d pwm_m_b_pins
ffff8000810f7c38 d pwm_l_b_pins
ffff8000810f7c40 d pwm_k_b_pins
ffff8000810f7c48 d pwm_j_b_pins
ffff8000810f7c50 d spif_wp_pins
ffff8000810f7c58 d spif_clk_pins
ffff8000810f7c60 d spif_mi_pins
ffff8000810f7c68 d spif_mo_pins
ffff8000810f7c70 d spif_hold_pins
ffff8000810f7c78 d pwm_i_b_pins
ffff8000810f7c80 d pwm_h_b_pins
ffff8000810f7c88 d pwm_g_b_pins
ffff8000810f7c90 d nand_ce0_pins
ffff8000810f7c98 d nand_cle_pins
ffff8000810f7ca0 d nand_ren_wr_pins
ffff8000810f7ca8 d nand_ale_pins
ffff8000810f7cb0 d nand_wen_clk_pins
ffff8000810f7cb8 d emmc_nand_ds_pins
ffff8000810f7cc0 d emmc_cmd_pins
ffff8000810f7cc8 d emmc_rst_pins
ffff8000810f7cd0 d emmc_clk_pins
ffff8000810f7cd8 d emmc_nand_d7_pins
ffff8000810f7ce0 d emmc_nand_d6_pins
ffff8000810f7ce8 d emmc_nand_d5_pins
ffff8000810f7cf0 d emmc_nand_d4_pins
ffff8000810f7cf8 d emmc_nand_d3_pins
ffff8000810f7d00 d emmc_nand_d2_pins
ffff8000810f7d08 d emmc_nand_d1_pins
ffff8000810f7d10 d emmc_nand_d0_pins
ffff8000810f7d18 d clk12_24_e_pins
ffff8000810f7d20 d i2c_slave_sda_pins
ffff8000810f7d28 d i2c_slave_scl_pins
ffff8000810f7d30 d clk_32k_in_pins
ffff8000810f7d38 d i2c0_scl_e_pins
ffff8000810f7d40 d i2c0_sda_e_pins
ffff8000810f7d48 d gen_clk_e_pins
ffff8000810f7d50 d i2c2_scl_pins
ffff8000810f7d58 d i2c2_sda_pins
ffff8000810f7d60 d pwm_b_pins
ffff8000810f7d68 d pwm_a_pins
ffff8000810f7d70 d c3_periphs_pins
ffff8000810f8298 d t7_pinctrl_dt_match
ffff8000810f8428 d t7_periphs_pinctrl_data
ffff8000810f8480 d t7_periphs_pmx_banks_data
ffff8000810f8490 d t7_periphs_pmx_banks
ffff8000810f85b0 d t7_periphs_banks
ffff8000810f8910 d t7_periphs_functions
ffff8000810f9060 d mic_mute_groups
ffff8000810f9070 d edp_b_groups
ffff8000810f9078 d edp_a_groups
ffff8000810f9080 d vx1_b_groups
ffff8000810f9090 d vx1_a_groups
ffff8000810f90a0 d sync_3d_groups
ffff8000810f90a8 d vsync_groups
ffff8000810f90b0 d hsync_groups
ffff8000810f90b8 d pcieck_groups
ffff8000810f90c8 d pdm_groups
ffff8000810f90f8 d mclk_groups
ffff8000810f9108 d tsin_d_groups
ffff8000810f9148 d tsin_c_groups
ffff8000810f9188 d tsin_b_groups
ffff8000810f91e8 d tsin_a_groups
ffff8000810f9208 d iso7816_groups
ffff8000810f9228 d eth_groups
ffff8000810f92a8 d clk25m_groups
ffff8000810f92b0 d spdif_in_groups
ffff8000810f92c0 d spdif_out_groups
ffff8000810f92d0 d rtc_clk_groups
ffff8000810f92e0 d wd_rsto_groups
ffff8000810f92e8 d remote_in_groups
ffff8000810f92f0 d remote_out_groups
ffff8000810f9300 d hdmitx_groups
ffff8000810f9328 d cec_b_groups
ffff8000810f9330 d cec_a_groups
ffff8000810f9338 d hdmirx_c_groups
ffff8000810f9358 d hdmirx_b_groups
ffff8000810f9378 d hdmirx_a_groups
ffff8000810f9398 d clk12_24_groups
ffff8000810f93a8 d i2c5_groups
ffff8000810f93b8 d i2c4_groups
ffff8000810f93d8 d i2c3_groups
ffff8000810f93f8 d i2c2_groups
ffff8000810f9428 d i2c1_groups
ffff8000810f9438 d i2c0_groups
ffff8000810f9458 d i2c1_ao_groups
ffff8000810f9468 d i2c0_ao_groups
ffff8000810f9488 d i2c0_slave_ao_groups
ffff8000810f9498 d tdm_groups
ffff8000810f9558 d pwm_vs_groups
ffff8000810f9568 d pwm_ao_g_groups
ffff8000810f9580 d pwm_ao_h_groups
ffff8000810f9590 d pwm_ao_f_groups
ffff8000810f9598 d pwm_ao_e_groups
ffff8000810f95a0 d pwm_ao_d_groups
ffff8000810f95a8 d pwm_ao_c_groups
ffff8000810f95b8 d pwm_ao_b_groups
ffff8000810f95c0 d pwm_ao_a_groups
ffff8000810f95c8 d pwm_ao_g_hiz_groups
ffff8000810f95d0 d pwm_ao_c_hiz_groups
ffff8000810f95d8 d pwm_f_groups
ffff8000810f95e0 d pwm_e_groups
ffff8000810f95e8 d pwm_d_groups
ffff8000810f95f0 d pwm_c_groups
ffff8000810f95f8 d pwm_b_groups
ffff8000810f9600 d pwm_a_groups
ffff8000810f9608 d spi5_groups
ffff8000810f9628 d spi4_groups
ffff8000810f9648 d spi3_groups
ffff8000810f9668 d spi2_groups
ffff8000810f9698 d spi1_groups
ffff8000810f96e8 d spi0_groups
ffff8000810f9718 d uart_ao_b_groups
ffff8000810f9738 d uart_ao_a_groups
ffff8000810f9788 d uart_f_groups
ffff8000810f97a8 d uart_e_groups
ffff8000810f97c8 d uart_d_groups
ffff8000810f9808 d uart_c_groups
ffff8000810f9828 d jtag_b_groups
ffff8000810f9848 d jtag_a_groups
ffff8000810f9868 d gen_clk_groups
ffff8000810f9878 d sdio_groups
ffff8000810f98a8 d sdcard_groups
ffff8000810f98d8 d nor_groups
ffff8000810f9908 d emmc_groups
ffff8000810f9960 d gpio_periphs_groups
ffff8000810f9e48 d t7_periphs_groups
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ffff8000810fe8d8 d uart_f_cts_pins
ffff8000810fe8e0 d uart_f_rx_pins
ffff8000810fe8e8 d uart_f_tx_pins
ffff8000810fe8f0 d pwm_vs_h_pins
ffff8000810fe8f8 d eth_act_led_pins
ffff8000810fe900 d eth_link_led_pins
ffff8000810fe908 d i2c4_sda_h_pins
ffff8000810fe910 d i2c4_sck_h_pins
ffff8000810fe918 d i2c3_sda_h_pins
ffff8000810fe920 d i2c3_sck_h_pins
ffff8000810fe928 d mic_mute_led_pins
ffff8000810fe930 d mic_mute_key_pins
ffff8000810fe938 d edp_b_hpd_pins
ffff8000810fe940 d edp_a_hpd_pins
ffff8000810fe948 d pwm_vs_y_pins
ffff8000810fe950 d vx1_b_lockn_pins
ffff8000810fe958 d vx1_a_lockn_pins
ffff8000810fe960 d vx1_b_htpdn_pins
ffff8000810fe968 d vx1_a_htpdn_pins
ffff8000810fe970 d sync_3d_out_pins
ffff8000810fe978 d pwm_f_pins
ffff8000810fe980 d vsync_pins
ffff8000810fe988 d hsync_pins
ffff8000810fe990 d pwm_e_pins
ffff8000810fe998 d pcieck_reqn_y_pins
ffff8000810fe9a0 d tsin_d_y_valid_pins
ffff8000810fe9a8 d tsin_d_y_clk_pins
ffff8000810fe9b0 d tsin_d_y_din0_pins
ffff8000810fe9b8 d tsin_d_y_sop_pins
ffff8000810fe9c0 d tsin_c_y_valid_pins
ffff8000810fe9c8 d tsin_c_y_clk_pins
ffff8000810fe9d0 d tsin_c_y_din0_pins
ffff8000810fe9d8 d tsin_c_y_sop_pins
ffff8000810fe9e0 d i2c5_sda_pins
ffff8000810fe9e8 d i2c5_sck_pins
ffff8000810fe9f0 d i2c4_sda_y_pins
ffff8000810fe9f8 d i2c4_sck_y_pins
ffff8000810fea00 d uart_d_rx_y_pins
ffff8000810fea08 d uart_d_tx_y_pins
ffff8000810fea10 d uart_d_rts_y_pins
ffff8000810fea18 d uart_d_cts_y_pins
ffff8000810fea20 d uart_e_rts_pins
ffff8000810fea28 d uart_e_cts_pins
ffff8000810fea30 d uart_e_rx_pins
ffff8000810fea38 d uart_e_tx_pins
ffff8000810fea40 d spi2_ss2_pins
ffff8000810fea48 d spi2_ss1_pins
ffff8000810fea50 d spi2_ss0_pins
ffff8000810fea58 d spi2_sclk_pins
ffff8000810fea60 d spi2_miso_pins
ffff8000810fea68 d spi2_mosi_pins
ffff8000810fea70 d i2c2_sck_m_pins
ffff8000810fea78 d i2c2_sda_m_pins
ffff8000810fea80 d uart_d_rts_m_pins
ffff8000810fea88 d uart_d_cts_m_pins
ffff8000810fea90 d uart_d_rx_m_pins
ffff8000810fea98 d uart_d_tx_m_pins
ffff8000810feaa0 d pdm_din1_m5_pins
ffff8000810feaa8 d pdm_din0_pins
ffff8000810feab0 d pdm_dclk_pins
ffff8000810feab8 d pdm_din3_pins
ffff8000810feac0 d pdm_din2_pins
ffff8000810feac8 d pdm_din1_m0_pins
ffff8000810fead0 d spi1_ss2_m_pins
ffff8000810fead8 d spi1_ss1_m_pins
ffff8000810feae0 d spi1_ss0_m_pins
ffff8000810feae8 d spi1_sclk_m_pins
ffff8000810feaf0 d spi1_miso_m_pins
ffff8000810feaf8 d spi1_mosi_m_pins
ffff8000810feb00 d i2c3_sck_m_pins
ffff8000810feb08 d i2c3_sda_m_pins
ffff8000810feb10 d tdm_fs3_pins
ffff8000810feb18 d tdm_sclk3_pins
ffff8000810feb20 d tdm_d15_pins
ffff8000810feb28 d tdm_d14_pins
ffff8000810feb30 d tdm_d13_pins
ffff8000810feb38 d tdm_d12_pins
ffff8000810feb40 d spi3_ss0_pins
ffff8000810feb48 d spi3_sclk_pins
ffff8000810feb50 d spi3_miso_pins
ffff8000810feb58 d spi3_mosi_pins
ffff8000810feb60 d i2c2_sda_t_pins
ffff8000810feb68 d i2c2_sck_t_pins
ffff8000810feb70 d i2c0_sda_t_pins
ffff8000810feb78 d i2c0_sck_t_pins
ffff8000810feb80 d tsin_a_valid_t_pins
ffff8000810feb88 d tsin_a_clk_t_pins
ffff8000810feb90 d tsin_a_din0_t_pins
ffff8000810feb98 d tsin_a_sop_t_pins
ffff8000810feba0 d iso7816_data_t_pins
ffff8000810feba8 d iso7816_clk_t_pins
ffff8000810febb0 d spdif_out_t_pins
ffff8000810febb8 d spdif_in_t_pins
ffff8000810febc0 d spi0_ss2_pins
ffff8000810febc8 d spi0_ss1_pins
ffff8000810febd0 d spi0_ss0_pins
ffff8000810febd8 d spi0_sclk_pins
ffff8000810febe0 d spi0_miso_pins
ffff8000810febe8 d spi0_mosi_pins
ffff8000810febf0 d i2c1_sda_pins
ffff8000810febf8 d i2c1_sck_pins
ffff8000810fec00 d tdm_fs2_pins
ffff8000810fec08 d tdm_sclk2_pins
ffff8000810fec10 d mclk2_pins
ffff8000810fec18 d tdm_d11_pins
ffff8000810fec20 d tdm_d10_pins
ffff8000810fec28 d tdm_d9_pins
ffff8000810fec30 d tdm_d8_pins
ffff8000810fec38 d tdm_d7_pins
ffff8000810fec40 d tdm_d6_pins
ffff8000810fec48 d tdm_d5_pins
ffff8000810fec50 d tdm_d4_pins
ffff8000810fec58 d tdm_d3_pins
ffff8000810fec60 d tdm_d2_pins
ffff8000810fec68 d tdm_fs1_pins
ffff8000810fec70 d tdm_sclk1_pins
ffff8000810fec78 d mclk1_pins
ffff8000810fec80 d spi5_ss0_pins
ffff8000810fec88 d spi5_sclk_pins
ffff8000810fec90 d spi5_miso_pins
ffff8000810fec98 d spi5_mosi_pins
ffff8000810feca0 d spi4_ss0_pins
ffff8000810feca8 d spi4_sclk_pins
ffff8000810fecb0 d spi4_miso_pins
ffff8000810fecb8 d spi4_mosi_pins
ffff8000810fecc0 d tsin_d_z_clk_pins
ffff8000810fecc8 d tsin_d_z_din0_pins
ffff8000810fecd0 d tsin_d_z_sop_pins
ffff8000810fecd8 d tsin_d_z_valid_pins
ffff8000810fece0 d tsin_c_z_clk_pins
ffff8000810fece8 d tsin_c_z_din0_pins
ffff8000810fecf0 d tsin_c_z_sop_pins
ffff8000810fecf8 d tsin_c_z_valid_pins
ffff8000810fed00 d tsin_b_din7_pins
ffff8000810fed08 d tsin_b_din6_pins
ffff8000810fed10 d tsin_b_din5_pins
ffff8000810fed18 d tsin_b_din4_pins
ffff8000810fed20 d tsin_b_din3_pins
ffff8000810fed28 d tsin_b_din2_pins
ffff8000810fed30 d tsin_b_din1_pins
ffff8000810fed38 d tsin_b_fail_pins
ffff8000810fed40 d tsin_b_clk_pins
ffff8000810fed48 d tsin_b_din0_pins
ffff8000810fed50 d tsin_b_sop_pins
ffff8000810fed58 d tsin_b_valid_pins
ffff8000810fed60 d iso7816_data_z_pins
ffff8000810fed68 d iso7816_clk_z_pins
ffff8000810fed70 d eth_txd3_rgmii_pins
ffff8000810fed78 d eth_txd2_rgmii_pins
ffff8000810fed80 d eth_txd1_pins
ffff8000810fed88 d eth_txd0_pins
ffff8000810fed90 d eth_txen_pins
ffff8000810fed98 d eth_rgmii_tx_clk_pins
ffff8000810feda0 d eth_rxd3_rgmii_pins
ffff8000810feda8 d eth_rxd2_rgmii_pins
ffff8000810fedb0 d eth_rxd1_pins
ffff8000810fedb8 d eth_rxd0_pins
ffff8000810fedc0 d eth_rx_dv_pins
ffff8000810fedc8 d eth_rgmii_rx_clk_pins
ffff8000810fedd0 d eth_mdc_pins
ffff8000810fedd8 d eth_mdio_pins
ffff8000810fede0 d clk12_24_e_pins
ffff8000810fede8 d rtc_clk_out_pins
ffff8000810fedf0 d i2c1_ao_sda_pins
ffff8000810fedf8 d i2c1_ao_sck_pins
ffff8000810fee00 d clk25m_pins
ffff8000810fee08 d i2c0_ao_sda_e_pins
ffff8000810fee10 d i2c0_ao_sck_e_pins
ffff8000810fee18 d pwm_ao_g_e_pins
ffff8000810fee20 d pwm_ao_f_pins
ffff8000810fee28 d pwm_ao_e_pins
ffff8000810fee30 d pwm_ao_d_pins
ffff8000810fee38 d pwm_ao_c_e_pins
ffff8000810fee40 d pwm_ao_b_pins
ffff8000810fee48 d pwm_ao_a_pins
ffff8000810fee50 d remote_out_d6_pins
ffff8000810fee58 d uart_ao_b_rts_pins
ffff8000810fee60 d pwm_ao_g_hiz_pins
ffff8000810fee68 d pwm_ao_c_hiz_pins
ffff8000810fee70 d uart_ao_b_cts_pins
ffff8000810fee78 d uart_ao_b_rx_pins
ffff8000810fee80 d uart_ao_b_tx_pins
ffff8000810fee88 d pwm_ao_h_d10_pins
ffff8000810fee90 d spdif_in_d_pins
ffff8000810fee98 d spdif_out_d_pins
ffff8000810feea0 d pwm_ao_g_d7_pins
ffff8000810feea8 d pwm_ao_c_d_pins
ffff8000810feeb0 d pwm_ao_h_d5_pins
ffff8000810feeb8 d rtc_clk_in_pins
ffff8000810feec0 d i2c0_slave_ao_sda_pins
ffff8000810feec8 d i2c0_slave_ao_sck_pins
ffff8000810feed0 d wd_rsto_pins
ffff8000810feed8 d pwm_ao_g_d11_pins
ffff8000810feee0 d gen_clk_out_d_pins
ffff8000810feee8 d jtag_a_tdo_pins
ffff8000810feef0 d jtag_a_tdi_pins
ffff8000810feef8 d jtag_a_tms_pins
ffff8000810fef00 d jtag_a_clk_pins
ffff8000810fef08 d remote_in_pins
ffff8000810fef10 d remote_out_d4_pins
ffff8000810fef18 d i2c0_ao_sda_d_pins
ffff8000810fef20 d i2c0_ao_sck_d_pins
ffff8000810fef28 d uart_ao_a_rx_d1_pins
ffff8000810fef30 d uart_ao_a_tx_d0_pins
ffff8000810fef38 d hdmitx_sck_w3_pins
ffff8000810fef40 d hdmitx_sda_w2_pins
ffff8000810fef48 d uart_ao_a_rx_w11_pins
ffff8000810fef50 d uart_ao_a_tx_w10_pins
ffff8000810fef58 d uart_ao_a_rx_w7_pins
ffff8000810fef60 d uart_ao_a_tx_w6_pins
ffff8000810fef68 d uart_ao_a_rx_w3_pins
ffff8000810fef70 d uart_ao_a_tx_w2_pins
ffff8000810fef78 d cec_b_pins
ffff8000810fef80 d hdmitx_hpd_in_pins
ffff8000810fef88 d hdmitx_sck_w14_pins
ffff8000810fef90 d hdmitx_sda_w13_pins
ffff8000810fef98 d cec_a_pins
ffff8000810fefa0 d hdmirx_b_sck_pins
ffff8000810fefa8 d hdmirx_b_sda_pins
ffff8000810fefb0 d hdmirx_b_det_pins
ffff8000810fefb8 d hdmirx_b_hpd_pins
ffff8000810fefc0 d hdmirx_c_sck_pins
ffff8000810fefc8 d hdmirx_c_sda_pins
ffff8000810fefd0 d hdmirx_c_det_pins
ffff8000810fefd8 d hdmirx_c_hpd_pins
ffff8000810fefe0 d hdmirx_a_sck_pins
ffff8000810fefe8 d hdmirx_a_sda_pins
ffff8000810feff0 d hdmirx_a_det_pins
ffff8000810feff8 d hdmirx_a_hpd_pins
ffff8000810ff000 d clk12_24_x_pins
ffff8000810ff008 d pwm_d_pins
ffff8000810ff010 d i2c2_sck_x_pins
ffff8000810ff018 d i2c2_sda_x_pins
ffff8000810ff020 d pwm_a_pins
ffff8000810ff028 d uart_c_rts_pins
ffff8000810ff030 d uart_c_cts_pins
ffff8000810ff038 d uart_c_rx_pins
ffff8000810ff040 d uart_c_tx_pins
ffff8000810ff048 d tdm_sclk0_pins
ffff8000810ff050 d tdm_fs0_pins
ffff8000810ff058 d tdm_d1_pins
ffff8000810ff060 d tdm_d0_pins
ffff8000810ff068 d pwm_c_pins
ffff8000810ff070 d pwm_b_pins
ffff8000810ff078 d sdio_cmd_pins
ffff8000810ff080 d sdio_clk_pins
ffff8000810ff088 d sdio_d3_pins
ffff8000810ff090 d sdio_d2_pins
ffff8000810ff098 d sdio_d1_pins
ffff8000810ff0a0 d sdio_d0_pins
ffff8000810ff0a8 d spi1_ss0_c_pins
ffff8000810ff0b0 d spi1_sclk_c_pins
ffff8000810ff0b8 d spi1_miso_c_pins
ffff8000810ff0c0 d spi1_mosi_c_pins
ffff8000810ff0c8 d jtag_b_tms_pins
ffff8000810ff0d0 d jtag_b_clk_pins
ffff8000810ff0d8 d uart_ao_a_tx_c_pins
ffff8000810ff0e0 d uart_ao_a_rx_c_pins
ffff8000810ff0e8 d jtag_b_tdi_pins
ffff8000810ff0f0 d jtag_b_tdo_pins
ffff8000810ff0f8 d gen_clk_out_c_pins
ffff8000810ff100 d sdcard_cmd_pins
ffff8000810ff108 d sdcard_clk_pins
ffff8000810ff110 d sdcard_d3_pins
ffff8000810ff118 d sdcard_d2_pins
ffff8000810ff120 d sdcard_d1_pins
ffff8000810ff128 d sdcard_d0_pins
ffff8000810ff130 d nor_cs_pins
ffff8000810ff138 d nor_wp_pins
ffff8000810ff140 d nor_c_pins
ffff8000810ff148 d nor_q_pins
ffff8000810ff150 d nor_d_pins
ffff8000810ff158 d nor_hold_pins
ffff8000810ff160 d emmc_nand_ds_pins
ffff8000810ff168 d emmc_cmd_pins
ffff8000810ff170 d emmc_clk_pins
ffff8000810ff178 d emmc_nand_d7_pins
ffff8000810ff180 d emmc_nand_d6_pins
ffff8000810ff188 d emmc_nand_d5_pins
ffff8000810ff190 d emmc_nand_d4_pins
ffff8000810ff198 d emmc_nand_d3_pins
ffff8000810ff1a0 d emmc_nand_d2_pins
ffff8000810ff1a8 d emmc_nand_d1_pins
ffff8000810ff1b0 d emmc_nand_d0_pins
ffff8000810ff1b8 d t7_periphs_pins
ffff800081100070 d mvebu_pinctrl_ops
ffff8000811000a0 d mvebu_pinmux_ops
ffff8000811000f8 d mvebu_pinconf_ops
ffff800081100138 d armada_ap806_mpp_controls
ffff800081100170 d armada_ap806_pinctrl_of_match
ffff800081100300 d armada_cp110_mpp_controls
ffff800081100338 d armada_cp110_pinctrl_of_match
ffff800081100720 d armada_37xx_pinctrl_regmap_config
ffff800081100858 d armada_37xx_pctrl_ops
ffff800081100888 d armada_37xx_pmx_ops
ffff8000811008e0 d armada_37xx_pinconf_ops
ffff800081100920 d armada_37xx_irqchip
ffff800081100a30 d __func__.0
ffff800081100a50 d __func__.1
ffff800081100a70 d __func__.2
ffff800081100a98 d armada_37xx_pinctrl_of_match
ffff800081100cf0 d armada_3700_pinctrl_pm_ops
ffff800081100da8 d armada_37xx_pin_sb
ffff800081100dc8 d armada_37xx_pin_nb
ffff800081100de8 d ac5_mpp_controls
ffff800081100e20 d ac5_pinctrl_of_match
ffff800081100fb0 d msm_pinctrl_ops
ffff800081100fe0 d msm_pinmux_ops
ffff800081101038 d msm_pinconf_ops
ffff800081101078 d msm_gpio_irq_chip
ffff800081101188 d pulls_no_keeper.1
ffff8000811011a0 d pulls_keeper.0
ffff8000811011c0 d __func__.2
ffff8000811011d8 D msm_pinctrl_dev_pm_ops
ffff800081101290 d sdm845_pinctrl
ffff8000811012f8 d sdm845_acpi_pinctrl
ffff800081101360 d sdm845_pinctrl_of_match
ffff8000811014f0 d sdm845_pinctrl_acpi_match
ffff800081101530 d sdm845_pdc_map
ffff800081101788 d sdm845_acpi_reserved_gpios
ffff8000811017b0 d sdm845_groups
ffff800081104300 d sdm845_functions
ffff800081105320 d tsif1_sync_groups
ffff800081105328 d m_voc_groups
ffff800081105330 d atest_usb10_groups
ffff800081105338 d wlan2_adc0_groups
ffff800081105340 d dbg_out_groups
ffff800081105348 d edp_lcd_groups
ffff800081105350 d ddr_pxi2_groups
ffff800081105360 d atest_usb11_groups
ffff800081105368 d wlan2_adc1_groups
ffff800081105370 d qup_l6_groups
ffff800081105390 d mdp_vsync_groups
ffff8000811053b8 d atest_usb12_groups
ffff8000811053c0 d wlan1_adc0_groups
ffff8000811053c8 d qup_l5_groups
ffff8000811053e8 d ddr_pxi1_groups
ffff8000811053f8 d atest_usb13_groups
ffff800081105400 d wlan1_adc1_groups
ffff800081105408 d qup_l4_groups
ffff800081105428 d atest_usb1_groups
ffff800081105430 d vsense_trigger_groups
ffff800081105438 d atest_tsens2_groups
ffff800081105440 d ddr_bist_groups
ffff800081105460 d ddr_pxi0_groups
ffff800081105470 d qdss_cti_groups
ffff8000811054b0 d qup9_groups
ffff8000811054d0 d gpio_groups
ffff800081105980 d qup0_groups
ffff8000811059a0 d mss_lte_groups
ffff8000811059b0 d pa_indicator_groups
ffff8000811059b8 d qlink_enable_groups
ffff8000811059c0 d qlink_request_groups
ffff8000811059c8 d adsp_ext_groups
ffff8000811059d0 d atest_char_groups
ffff8000811059f8 d nav_pps_groups
ffff800081105a48 d edp_hot_groups
ffff800081105a50 d uim_batt_groups
ffff800081105a58 d uim1_present_groups
ffff800081105a60 d uim1_reset_groups
ffff800081105a68 d uim1_clk_groups
ffff800081105a70 d uim1_data_groups
ffff800081105a78 d uim2_present_groups
ffff800081105a80 d uim2_reset_groups
ffff800081105a88 d uim2_clk_groups
ffff800081105a90 d qup13_groups
ffff800081105ab0 d uim2_data_groups
ffff800081105ab8 d prng_rosc_groups
ffff800081105ac0 d pci_e1_groups
ffff800081105ad0 d ldo_update_groups
ffff800081105ad8 d ldo_en_groups
ffff800081105ae0 d tsif2_sync_groups
ffff800081105ae8 d qspi_clk_groups
ffff800081105af0 d tsif2_data_groups
ffff800081105af8 d tsif2_en_groups
ffff800081105b00 d qup7_groups
ffff800081105b20 d sdc4_clk_groups
ffff800081105b28 d tsif2_clk_groups
ffff800081105b30 d tgu_ch2_groups
ffff800081105b38 d vfr_1_groups
ffff800081105b40 d sdc4_data_groups
ffff800081105b60 d tsif2_error_groups
ffff800081105b68 d tgu_ch1_groups
ffff800081105b70 d qspi_data_groups
ffff800081105b90 d sdc4_cmd_groups
ffff800081105b98 d tsif1_data_groups
ffff800081105ba0 d tgu_ch0_groups
ffff800081105ba8 d mdp_vsync3_groups
ffff800081105bb0 d mdp_vsync2_groups
ffff800081105bb8 d mdp_vsync1_groups
ffff800081105bc0 d mdp_vsync0_groups
ffff800081105bc8 d tsif1_en_groups
ffff800081105bd0 d tgu_ch3_groups
ffff800081105bd8 d qspi_cs_groups
ffff800081105be8 d qup4_groups
ffff800081105c08 d tsif1_clk_groups
ffff800081105c10 d qup5_groups
ffff800081105c30 d qup15_groups
ffff800081105c50 d sec_mi2s_groups
ffff800081105c78 d atest_usb20_groups
ffff800081105c80 d atest_usb21_groups
ffff800081105c88 d atest_usb22_groups
ffff800081105c90 d atest_usb23_groups
ffff800081105c98 d ter_mi2s_groups
ffff800081105cc0 d atest_usb2_groups
ffff800081105cc8 d btfm_slimbus_groups
ffff800081105cd8 d tsense_pwm2_groups
ffff800081105ce0 d tsense_pwm1_groups
ffff800081105ce8 d audio_ref_groups
ffff800081105cf0 d spkr_i2s_groups
ffff800081105d10 d pri_mi2s_ws_groups
ffff800081105d18 d qup8_groups
ffff800081105d38 d sp_cmu_groups
ffff800081105d40 d pri_mi2s_groups
ffff800081105d60 d cri_trng_groups
ffff800081105d68 d cri_trng1_groups
ffff800081105d70 d cri_trng0_groups
ffff800081105d78 d gcc_gp1_groups
ffff800081105d88 d qua_mi2s_groups
ffff800081105dc0 d qup10_groups
ffff800081105de0 d qup12_groups
ffff800081105e00 d qup6_groups
ffff800081105e20 d qup3_groups
ffff800081105e40 d tsif1_error_groups
ffff800081105e48 d sd_write_groups
ffff800081105e50 d lpass_slimbus_groups
ffff800081105e70 d usb_phy_groups
ffff800081105e78 d agera_pll_groups
ffff800081105e80 d atest_tsens_groups
ffff800081105e88 d pll_bist_groups
ffff800081105e90 d jitter_bist_groups
ffff800081105e98 d pci_e0_groups
ffff800081105ea8 d qup14_groups
ffff800081105ec8 d qup11_groups
ffff800081105ee8 d phase_flag_groups
ffff800081105fe8 d qup2_groups
ffff800081106008 d cci_timer4_groups
ffff800081106010 d cci_async_groups
ffff800081106028 d cci_timer3_groups
ffff800081106030 d cci_timer2_groups
ffff800081106038 d gcc_gp3_groups
ffff800081106048 d cci_timer1_groups
ffff800081106050 d gcc_gp2_groups
ffff800081106060 d cci_timer0_groups
ffff800081106068 d qup1_groups
ffff800081106088 d cci_i2c_groups
ffff8000811060a8 d pll_reset_groups
ffff8000811060b0 d qdss_groups
ffff8000811061d0 d pll_bypassnl_groups
ffff8000811061d8 d cam_mclk_groups
ffff8000811061f8 d ddr_pxi3_groups
ffff800081106208 d sdc2_data_pins
ffff800081106210 d sdc2_cmd_pins
ffff800081106218 d sdc2_clk_pins
ffff800081106220 d ufs_reset_pins
ffff800081106228 d gpio149_pins
ffff800081106230 d gpio148_pins
ffff800081106238 d gpio147_pins
ffff800081106240 d gpio146_pins
ffff800081106248 d gpio145_pins
ffff800081106250 d gpio144_pins
ffff800081106258 d gpio143_pins
ffff800081106260 d gpio142_pins
ffff800081106268 d gpio141_pins
ffff800081106270 d gpio140_pins
ffff800081106278 d gpio139_pins
ffff800081106280 d gpio138_pins
ffff800081106288 d gpio137_pins
ffff800081106290 d gpio136_pins
ffff800081106298 d gpio135_pins
ffff8000811062a0 d gpio134_pins
ffff8000811062a8 d gpio133_pins
ffff8000811062b0 d gpio132_pins
ffff8000811062b8 d gpio131_pins
ffff8000811062c0 d gpio130_pins
ffff8000811062c8 d gpio129_pins
ffff8000811062d0 d gpio128_pins
ffff8000811062d8 d gpio127_pins
ffff8000811062e0 d gpio126_pins
ffff8000811062e8 d gpio125_pins
ffff8000811062f0 d gpio124_pins
ffff8000811062f8 d gpio123_pins
ffff800081106300 d gpio122_pins
ffff800081106308 d gpio121_pins
ffff800081106310 d gpio120_pins
ffff800081106318 d gpio119_pins
ffff800081106320 d gpio118_pins
ffff800081106328 d gpio117_pins
ffff800081106330 d gpio116_pins
ffff800081106338 d gpio115_pins
ffff800081106340 d gpio114_pins
ffff800081106348 d gpio113_pins
ffff800081106350 d gpio112_pins
ffff800081106358 d gpio111_pins
ffff800081106360 d gpio110_pins
ffff800081106368 d gpio109_pins
ffff800081106370 d gpio108_pins
ffff800081106378 d gpio107_pins
ffff800081106380 d gpio106_pins
ffff800081106388 d gpio105_pins
ffff800081106390 d gpio104_pins
ffff800081106398 d gpio103_pins
ffff8000811063a0 d gpio102_pins
ffff8000811063a8 d gpio101_pins
ffff8000811063b0 d gpio100_pins
ffff8000811063b8 d gpio99_pins
ffff8000811063c0 d gpio98_pins
ffff8000811063c8 d gpio97_pins
ffff8000811063d0 d gpio96_pins
ffff8000811063d8 d gpio95_pins
ffff8000811063e0 d gpio94_pins
ffff8000811063e8 d gpio93_pins
ffff8000811063f0 d gpio92_pins
ffff8000811063f8 d gpio91_pins
ffff800081106400 d gpio90_pins
ffff800081106408 d gpio89_pins
ffff800081106410 d gpio88_pins
ffff800081106418 d gpio87_pins
ffff800081106420 d gpio86_pins
ffff800081106428 d gpio85_pins
ffff800081106430 d gpio84_pins
ffff800081106438 d gpio83_pins
ffff800081106440 d gpio82_pins
ffff800081106448 d gpio81_pins
ffff800081106450 d gpio80_pins
ffff800081106458 d gpio79_pins
ffff800081106460 d gpio78_pins
ffff800081106468 d gpio77_pins
ffff800081106470 d gpio76_pins
ffff800081106478 d gpio75_pins
ffff800081106480 d gpio74_pins
ffff800081106488 d gpio73_pins
ffff800081106490 d gpio72_pins
ffff800081106498 d gpio71_pins
ffff8000811064a0 d gpio70_pins
ffff8000811064a8 d gpio69_pins
ffff8000811064b0 d gpio68_pins
ffff8000811064b8 d gpio67_pins
ffff8000811064c0 d gpio66_pins
ffff8000811064c8 d gpio65_pins
ffff8000811064d0 d gpio64_pins
ffff8000811064d8 d gpio63_pins
ffff8000811064e0 d gpio62_pins
ffff8000811064e8 d gpio61_pins
ffff8000811064f0 d gpio60_pins
ffff8000811064f8 d gpio59_pins
ffff800081106500 d gpio58_pins
ffff800081106508 d gpio57_pins
ffff800081106510 d gpio56_pins
ffff800081106518 d gpio55_pins
ffff800081106520 d gpio54_pins
ffff800081106528 d gpio53_pins
ffff800081106530 d gpio52_pins
ffff800081106538 d gpio51_pins
ffff800081106540 d gpio50_pins
ffff800081106548 d gpio49_pins
ffff800081106550 d gpio48_pins
ffff800081106558 d gpio47_pins
ffff800081106560 d gpio46_pins
ffff800081106568 d gpio45_pins
ffff800081106570 d gpio44_pins
ffff800081106578 d gpio43_pins
ffff800081106580 d gpio42_pins
ffff800081106588 d gpio41_pins
ffff800081106590 d gpio40_pins
ffff800081106598 d gpio39_pins
ffff8000811065a0 d gpio38_pins
ffff8000811065a8 d gpio37_pins
ffff8000811065b0 d gpio36_pins
ffff8000811065b8 d gpio35_pins
ffff8000811065c0 d gpio34_pins
ffff8000811065c8 d gpio33_pins
ffff8000811065d0 d gpio32_pins
ffff8000811065d8 d gpio31_pins
ffff8000811065e0 d gpio30_pins
ffff8000811065e8 d gpio29_pins
ffff8000811065f0 d gpio28_pins
ffff8000811065f8 d gpio27_pins
ffff800081106600 d gpio26_pins
ffff800081106608 d gpio25_pins
ffff800081106610 d gpio24_pins
ffff800081106618 d gpio23_pins
ffff800081106620 d gpio22_pins
ffff800081106628 d gpio21_pins
ffff800081106630 d gpio20_pins
ffff800081106638 d gpio19_pins
ffff800081106640 d gpio18_pins
ffff800081106648 d gpio17_pins
ffff800081106650 d gpio16_pins
ffff800081106658 d gpio15_pins
ffff800081106660 d gpio14_pins
ffff800081106668 d gpio13_pins
ffff800081106670 d gpio12_pins
ffff800081106678 d gpio11_pins
ffff800081106680 d gpio10_pins
ffff800081106688 d gpio9_pins
ffff800081106690 d gpio8_pins
ffff800081106698 d gpio7_pins
ffff8000811066a0 d gpio6_pins
ffff8000811066a8 d gpio5_pins
ffff8000811066b0 d gpio4_pins
ffff8000811066b8 d gpio3_pins
ffff8000811066c0 d gpio2_pins
ffff8000811066c8 d gpio1_pins
ffff8000811066d0 d gpio0_pins
ffff8000811066d8 d sdm845_pins
ffff800081107548 d cfg_params
ffff800081107598 d samsung_pctrl_ops
ffff8000811075c8 d samsung_pinmux_ops
ffff800081107620 d samsung_pinconf_ops
ffff800081107660 d reg_names
ffff800081107690 d __func__.0
ffff8000811076a8 d __func__.1
ffff8000811076c0 d samsung_pinctrl_pm_ops
ffff800081107778 d samsung_pinctrl_dt_match
ffff800081108330 d exynos_eint_irqd_ops
ffff800081108380 d exynos_wkup_irq_ids
ffff8000811089c0 d __func__.0
ffff8000811089e0 d __func__.1
ffff8000811089f8 d __func__.2
ffff800081108a10 d __func__.3
ffff800081108a30 d __func__.4
ffff800081108a48 d __func__.5
ffff800081108a60 d __func__.6
ffff800081108a88 d gs101_pin_hsi2
ffff800081108b30 d gs101_pin_hsi1
ffff800081108ba0 d gs101_pin_peric1
ffff800081108d60 d gs101_pin_peric0
ffff8000811091c0 d gs101_pin_gsactrl
ffff8000811091f8 d gs101_pin_gsacore
ffff8000811092a0 d gs101_pin_far_alive
ffff800081109380 d gs101_pin_alive
ffff800081109540 d exynosautov920_pin_ctrl
ffff800081109740 d exynosautov920_pin_banks7
ffff800081109938 d exynosautov920_pin_banks6
ffff800081109b68 d exynosautov920_pin_banks5
ffff800081109ba0 d exynosautov920_pin_banks4
ffff800081109c80 d exynosautov920_pin_banks3
ffff800081109cb8 d exynosautov920_pin_banks2
ffff800081109d28 d exynosautov920_pin_banks1
ffff800081109eb0 d exynosautov920_pin_banks0
ffff800081109f58 d exynos5433_fsys_retention_regs
ffff800081109f68 d exynos5433_audio_retention_regs
ffff800081109f70 d exynos5433_retention_regs
ffff800081109f98 d exynos2200_pin_ctrl
ffff80008110a1d8 d artpec_bank_type_off
ffff80008110a1e8 d exynos8895_bank_type_off
ffff80008110a1f8 d exynos850_bank_type_alive
ffff80008110a208 d exynos850_bank_type_off
ffff80008110a218 d exynos7870_bank_type_alive
ffff80008110a228 d exynos5433_bank_type_alive
ffff80008110a238 d exynos5433_bank_type_off
ffff80008110a248 d bank_type_alive
ffff80008110a258 d bank_type_off
ffff80008110a268 d sunxi_pinctrl_irq_domain_ops
ffff80008110a2b8 d sunxi_pconf_ops
ffff80008110a2f8 d sunxi_pctrl_ops
ffff80008110a328 d sunxi_pmx_ops
ffff80008110a380 d __func__.0
ffff80008110a3a0 d a64_pinctrl_data
ffff80008110a3c8 d a64_pinctrl_match
ffff80008110a558 d a64_pins
ffff80008110b570 d sun50i_a64_r_pinctrl_data
ffff80008110b598 d sun50i_a64_r_pinctrl_match
ffff80008110b728 d sun50i_a64_r_pins
ffff80008110b930 d a100_pinctrl_data
ffff80008110b958 d a100_pinctrl_match
ffff80008110bae8 d a100_irq_bank_map
ffff80008110bb08 d a100_pins
ffff80008110cb20 d a100_r_pinctrl_data
ffff80008110cb48 d a100_r_pinctrl_match
ffff80008110ccd8 d a100_r_pins
ffff80008110ceb8 d sun8i_h3_r_pinctrl_data
ffff80008110cee0 d sun8i_h3_r_pinctrl_match
ffff80008110d070 d sun8i_h3_r_pins
ffff80008110d250 d sun50i_h5_pinctrl_data_broken
ffff80008110d278 d sun50i_h5_pinctrl_data
ffff80008110d2a0 d sun50i_h5_pinctrl_match
ffff80008110d430 d sun50i_h5_pins
ffff80008110e2e0 d h6_pinctrl_data
ffff80008110e308 d h6_pinctrl_match
ffff80008110e498 d h6_irq_bank_map
ffff80008110e4a8 d h6_pins
ffff80008110f588 d sun50i_h6_r_pinctrl_data
ffff80008110f5b0 d sun50i_h6_r_pinctrl_match
ffff80008110f740 d sun50i_h6_r_pins
ffff80008110f9c0 d h616_pinctrl_data
ffff80008110f9e8 d h616_pinctrl_match
ffff80008110fb78 d h616_irq_bank_map
ffff80008110fb98 d h616_pins
ffff800081111100 d sun50i_h616_r_pinctrl_data
ffff800081111128 d sun50i_h616_r_pinctrl_match
ffff8000811112b8 d sun50i_h616_r_pins
ffff800081111308 d a523_irq_bank_muxes
ffff800081111318 d a523_nr_bank_pins
ffff800081111328 d a523_pinctrl_match
ffff8000811114b8 d a523_irq_bank_map
ffff8000811114e0 d a523_r_irq_bank_muxes
ffff8000811114f0 d a523_r_nr_bank_pins
ffff800081111500 d a523_r_pinctrl_match
ffff800081111690 d a523_r_irq_bank_map
ffff8000811116b8 d cfg_params
ffff8000811117c8 d tegra_pinctrl_ops
ffff8000811117f8 d tegra_pinmux_ops
ffff800081111850 d tegra_pinconf_ops
ffff800081111890 d __func__.0
ffff8000811118a8 D tegra_pinctrl_pm
ffff800081111960 d tegra124_pinctrl
ffff8000811119a0 d tegra124_pinctrl_of_match
ffff800081111b30 d tegra124_groups
ffff800081115530 d tegra124_functions
ffff8000811157e0 d mipi_pad_ctrl_dsi_b_pins
ffff800081115808 d drive_ao4_pins
ffff800081115810 d drive_sdio4_pins
ffff800081115818 d drive_hv0_pins
ffff800081115820 d drive_ao0_pins
ffff800081115828 d drive_ao3_pins
ffff800081115830 d drive_usb_vbus_en_pins
ffff800081115838 d drive_dap5_pins
ffff800081115848 d drive_at6_pins
ffff800081115870 d drive_cec_pins
ffff800081115878 d drive_dev3_pins
ffff800081115880 d drive_gpv_pins
ffff8000811158a0 d drive_uda_pins
ffff8000811158b0 d drive_owr_pins
ffff8000811158b8 d drive_gmh_pins
ffff8000811158c0 d drive_gmg_pins
ffff8000811158c8 d drive_gmf_pins
ffff8000811158d8 d drive_gme_pins
ffff8000811158f0 d drive_gma_pins
ffff800081115918 d drive_ddc_pins
ffff800081115920 d drive_sdio1_pins
ffff800081115938 d drive_uart3_pins
ffff800081115948 d drive_uart2_pins
ffff800081115958 d drive_uab_pins
ffff800081115970 d drive_uaa_pins
ffff800081115980 d drive_spi_pins
ffff8000811159a8 d drive_sdio3_pins
ffff8000811159c8 d drive_dbg_pins
ffff8000811159f0 d drive_dap4_pins
ffff800081115a00 d drive_dap3_pins
ffff800081115a10 d drive_dap2_pins
ffff800081115a20 d drive_dap1_pins
ffff800081115a30 d drive_cdev2_pins
ffff800081115a38 d drive_cdev1_pins
ffff800081115a40 d drive_at5_pins
ffff800081115a48 d drive_at4_pins
ffff800081115a60 d drive_at3_pins
ffff800081115a68 d drive_at2_pins
ffff800081115aa8 d drive_at1_pins
ffff800081115ab8 d drive_ao2_pins
ffff800081115b18 d drive_ao1_pins
ffff800081115b40 d jtag_rtck_pins
ffff800081115b48 d clk_32k_in_pins
ffff800081115b50 d owr_pins
ffff800081115b58 d reset_out_n_pins
ffff800081115b60 d gmi_clk_lb_pins
ffff800081115b68 d pwr_int_n_pins
ffff800081115b70 d cpu_pwr_req_pins
ffff800081115b78 d core_pwr_req_pins
ffff800081115b80 d pff2_pins
ffff800081115b88 d usb_vbus_en2_pff1_pins
ffff800081115b90 d dp_hpd_pff0_pins
ffff800081115b98 d sdmmc3_clk_lb_in_pee5_pins
ffff800081115ba0 d sdmmc3_clk_lb_out_pee4_pins
ffff800081115ba8 d hdmi_cec_pee3_pins
ffff800081115bb0 d dap_mclk1_req_pee2_pins
ffff800081115bb8 d clk3_req_pee1_pins
ffff800081115bc0 d clk3_out_pee0_pins
ffff800081115bc8 d pex_l1_clkreq_n_pdd6_pins
ffff800081115bd0 d pex_l1_rst_n_pdd5_pins
ffff800081115bd8 d pex_wake_n_pdd3_pins
ffff800081115be0 d pex_l0_clkreq_n_pdd2_pins
ffff800081115be8 d pex_l0_rst_n_pdd1_pins
ffff800081115bf0 d clk2_req_pcc5_pins
ffff800081115bf8 d sdmmc4_clk_pcc4_pins
ffff800081115c00 d pcc2_pins
ffff800081115c08 d pcc1_pins
ffff800081115c10 d cam_mclk_pcc0_pins
ffff800081115c18 d pbb7_pins
ffff800081115c20 d pbb6_pins
ffff800081115c28 d pbb5_pins
ffff800081115c30 d pbb4_pins
ffff800081115c38 d pbb3_pins
ffff800081115c40 d cam_i2c_sda_pbb2_pins
ffff800081115c48 d cam_i2c_scl_pbb1_pins
ffff800081115c50 d pbb0_pins
ffff800081115c58 d sdmmc4_dat7_paa7_pins
ffff800081115c60 d sdmmc4_dat6_paa6_pins
ffff800081115c68 d sdmmc4_dat5_paa5_pins
ffff800081115c70 d sdmmc4_dat4_paa4_pins
ffff800081115c78 d sdmmc4_dat3_paa3_pins
ffff800081115c80 d sdmmc4_dat2_paa2_pins
ffff800081115c88 d sdmmc4_dat1_paa1_pins
ffff800081115c90 d sdmmc4_dat0_paa0_pins
ffff800081115c98 d pwr_i2c_sda_pz7_pins
ffff800081115ca0 d pwr_i2c_scl_pz6_pins
ffff800081115ca8 d sdmmc1_cmd_pz1_pins
ffff800081115cb0 d sdmmc1_clk_pz0_pins
ffff800081115cb8 d sdmmc1_dat0_py7_pins
ffff800081115cc0 d sdmmc1_dat1_py6_pins
ffff800081115cc8 d sdmmc1_dat2_py5_pins
ffff800081115cd0 d sdmmc1_dat3_py4_pins
ffff800081115cd8 d ulpi_stp_py3_pins
ffff800081115ce0 d ulpi_nxt_py2_pins
ffff800081115ce8 d ulpi_dir_py1_pins
ffff800081115cf0 d ulpi_clk_py0_pins
ffff800081115cf8 d gpio_x7_aud_px7_pins
ffff800081115d00 d gpio_x6_aud_px6_pins
ffff800081115d08 d gpio_x5_aud_px5_pins
ffff800081115d10 d gpio_x4_aud_px4_pins
ffff800081115d18 d gpio_x3_aud_px3_pins
ffff800081115d20 d dvfs_clk_px2_pins
ffff800081115d28 d gpio_x1_aud_px1_pins
ffff800081115d30 d dvfs_pwm_px0_pins
ffff800081115d38 d uart3_rxd_pw7_pins
ffff800081115d40 d uart3_txd_pw6_pins
ffff800081115d48 d clk2_out_pw5_pins
ffff800081115d50 d dap_mclk1_pw4_pins
ffff800081115d58 d gpio_w3_aud_pw3_pins
ffff800081115d60 d gpio_w2_aud_pw2_pins
ffff800081115d68 d ddc_sda_pv5_pins
ffff800081115d70 d ddc_scl_pv4_pins
ffff800081115d78 d sdmmc1_wp_n_pv3_pins
ffff800081115d80 d sdmmc3_cd_n_pv2_pins
ffff800081115d88 d pv1_pins
ffff800081115d90 d pv0_pins
ffff800081115d98 d pu6_pins
ffff800081115da0 d pu5_pins
ffff800081115da8 d pu4_pins
ffff800081115db0 d pu3_pins
ffff800081115db8 d pu2_pins
ffff800081115dc0 d pu1_pins
ffff800081115dc8 d pu0_pins
ffff800081115dd0 d sdmmc4_cmd_pt7_pins
ffff800081115dd8 d gen2_i2c_sda_pt6_pins
ffff800081115de0 d gen2_i2c_scl_pt5_pins
ffff800081115de8 d kb_row17_pt1_pins
ffff800081115df0 d kb_row16_pt0_pins
ffff800081115df8 d kb_row15_ps7_pins
ffff800081115e00 d kb_row14_ps6_pins
ffff800081115e08 d kb_row13_ps5_pins
ffff800081115e10 d kb_row12_ps4_pins
ffff800081115e18 d kb_row11_ps3_pins
ffff800081115e20 d kb_row10_ps2_pins
ffff800081115e28 d kb_row9_ps1_pins
ffff800081115e30 d kb_row8_ps0_pins
ffff800081115e38 d kb_row7_pr7_pins
ffff800081115e40 d kb_row6_pr6_pins
ffff800081115e48 d kb_row5_pr5_pins
ffff800081115e50 d kb_row4_pr4_pins
ffff800081115e58 d kb_row3_pr3_pins
ffff800081115e60 d kb_row2_pr2_pins
ffff800081115e68 d kb_row1_pr1_pins
ffff800081115e70 d kb_row0_pr0_pins
ffff800081115e78 d kb_col7_pq7_pins
ffff800081115e80 d kb_col6_pq6_pins
ffff800081115e88 d kb_col5_pq5_pins
ffff800081115e90 d kb_col4_pq4_pins
ffff800081115e98 d kb_col3_pq3_pins
ffff800081115ea0 d kb_col2_pq2_pins
ffff800081115ea8 d kb_col1_pq1_pins
ffff800081115eb0 d kb_col0_pq0_pins
ffff800081115eb8 d dap4_sclk_pp7_pins
ffff800081115ec0 d dap4_dout_pp6_pins
ffff800081115ec8 d dap4_din_pp5_pins
ffff800081115ed0 d dap4_fs_pp4_pins
ffff800081115ed8 d dap3_sclk_pp3_pins
ffff800081115ee0 d dap3_dout_pp2_pins
ffff800081115ee8 d dap3_din_pp1_pins
ffff800081115ef0 d dap3_fs_pp0_pins
ffff800081115ef8 d ulpi_data6_po7_pins
ffff800081115f00 d ulpi_data5_po6_pins
ffff800081115f08 d ulpi_data4_po5_pins
ffff800081115f10 d ulpi_data3_po4_pins
ffff800081115f18 d ulpi_data2_po3_pins
ffff800081115f20 d ulpi_data1_po2_pins
ffff800081115f28 d ulpi_data0_po1_pins
ffff800081115f30 d ulpi_data7_po0_pins
ffff800081115f38 d hdmi_int_pn7_pins
ffff800081115f40 d usb_vbus_en1_pn5_pins
ffff800081115f48 d usb_vbus_en0_pn4_pins
ffff800081115f50 d dap1_sclk_pn3_pins
ffff800081115f58 d dap1_dout_pn2_pins
ffff800081115f60 d dap1_din_pn1_pins
ffff800081115f68 d dap1_fs_pn0_pins
ffff800081115f70 d pk7_pins
ffff800081115f78 d spdif_in_pk6_pins
ffff800081115f80 d spdif_out_pk5_pins
ffff800081115f88 d pk4_pins
ffff800081115f90 d pk3_pins
ffff800081115f98 d pk2_pins
ffff800081115fa0 d pk1_pins
ffff800081115fa8 d pk0_pins
ffff800081115fb0 d pj7_pins
ffff800081115fb8 d uart2_rts_n_pj6_pins
ffff800081115fc0 d uart2_cts_n_pj5_pins
ffff800081115fc8 d pj2_pins
ffff800081115fd0 d pj0_pins
ffff800081115fd8 d pi7_pins
ffff800081115fe0 d pi6_pins
ffff800081115fe8 d pi5_pins
ffff800081115ff0 d pi4_pins
ffff800081115ff8 d pi3_pins
ffff800081116000 d pi2_pins
ffff800081116008 d pi1_pins
ffff800081116010 d pi0_pins
ffff800081116018 d ph7_pins
ffff800081116020 d ph6_pins
ffff800081116028 d ph5_pins
ffff800081116030 d ph4_pins
ffff800081116038 d ph3_pins
ffff800081116040 d ph2_pins
ffff800081116048 d ph1_pins
ffff800081116050 d ph0_pins
ffff800081116058 d pg7_pins
ffff800081116060 d pg6_pins
ffff800081116068 d pg5_pins
ffff800081116070 d pg4_pins
ffff800081116078 d pg3_pins
ffff800081116080 d pg2_pins
ffff800081116088 d pg1_pins
ffff800081116090 d pg0_pins
ffff800081116098 d pc7_pins
ffff8000811160a0 d gen1_i2c_sda_pc5_pins
ffff8000811160a8 d gen1_i2c_scl_pc4_pins
ffff8000811160b0 d uart2_rxd_pc3_pins
ffff8000811160b8 d uart2_txd_pc2_pins
ffff8000811160c0 d uart3_rts_n_pc0_pins
ffff8000811160c8 d sdmmc3_dat0_pb7_pins
ffff8000811160d0 d sdmmc3_dat1_pb6_pins
ffff8000811160d8 d sdmmc3_dat2_pb5_pins
ffff8000811160e0 d sdmmc3_dat3_pb4_pins
ffff8000811160e8 d pb1_pins
ffff8000811160f0 d pb0_pins
ffff8000811160f8 d sdmmc3_cmd_pa7_pins
ffff800081116100 d sdmmc3_clk_pa6_pins
ffff800081116108 d dap2_dout_pa5_pins
ffff800081116110 d dap2_din_pa4_pins
ffff800081116118 d dap2_sclk_pa3_pins
ffff800081116120 d dap2_fs_pa2_pins
ffff800081116128 d uart3_cts_n_pa1_pins
ffff800081116130 d clk_32k_out_pa0_pins
ffff800081116138 d tegra124_pins
ffff800081117410 d tegra210_pinctrl
ffff800081117450 d tegra210_pinctrl_of_match
ffff8000811175e0 d tegra210_groups
ffff80008111a4a0 d tegra210_functions
ffff80008111a6e8 d drive_sdmmc3_pins
ffff80008111a6e8 d drive_sdmmc4_pins
ffff80008111a700 d drive_sdmmc1_pins
ffff80008111a700 d drive_sdmmc2_pins
ffff80008111a718 d drive_pz5_pins
ffff80008111a720 d drive_pz4_pins
ffff80008111a728 d drive_pz3_pins
ffff80008111a730 d drive_pz2_pins
ffff80008111a738 d drive_pz1_pins
ffff80008111a740 d drive_pz0_pins
ffff80008111a748 d drive_pl1_pins
ffff80008111a750 d drive_pl0_pins
ffff80008111a758 d drive_pk7_pins
ffff80008111a760 d drive_pk6_pins
ffff80008111a768 d drive_pk5_pins
ffff80008111a770 d drive_pk4_pins
ffff80008111a778 d drive_pk3_pins
ffff80008111a780 d drive_pk2_pins
ffff80008111a788 d drive_pk1_pins
ffff80008111a790 d drive_pk0_pins
ffff80008111a798 d drive_ph6_pins
ffff80008111a7a0 d drive_pe7_pins
ffff80008111a7a8 d drive_pe6_pins
ffff80008111a7b0 d drive_pcc7_pins
ffff80008111a7b8 d drive_pa6_pins
ffff80008111a7c0 d shutdown_pins
ffff80008111a7c8 d clk_req_pins
ffff80008111a7d0 d batt_bcl_pins
ffff80008111a7d8 d jtag_rtck_pins
ffff80008111a7e0 d clk_32k_in_pins
ffff80008111a7e8 d pwr_int_n_pins
ffff80008111a7f0 d cpu_pwr_req_pins
ffff80008111a7f8 d core_pwr_req_pins
ffff80008111a800 d qspi_io3_pee5_pins
ffff80008111a808 d qspi_io2_pee4_pins
ffff80008111a810 d qspi_io1_pee3_pins
ffff80008111a818 d qspi_io0_pee2_pins
ffff80008111a820 d qspi_cs_n_pee1_pins
ffff80008111a828 d qspi_sck_pee0_pins
ffff80008111a830 d spi2_cs1_pdd0_pins
ffff80008111a838 d pcc7_pins
ffff80008111a840 d dp_hpd0_pcc6_pins
ffff80008111a848 d usb_vbus_en1_pcc5_pins
ffff80008111a850 d usb_vbus_en0_pcc4_pins
ffff80008111a858 d spdif_in_pcc3_pins
ffff80008111a860 d spdif_out_pcc2_pins
ffff80008111a868 d hdmi_int_dp_hpd_pcc1_pins
ffff80008111a870 d hdmi_cec_pcc0_pins
ffff80008111a878 d gpio_x3_aud_pbb4_pins
ffff80008111a880 d gpio_x1_aud_pbb3_pins
ffff80008111a888 d dvfs_clk_pbb2_pins
ffff80008111a890 d dvfs_pwm_pbb1_pins
ffff80008111a898 d aud_mclk_pbb0_pins
ffff80008111a8a0 d dap2_dout_paa3_pins
ffff80008111a8a8 d dap2_din_paa2_pins
ffff80008111a8b0 d dap2_sclk_paa1_pins
ffff80008111a8b8 d dap2_fs_paa0_pins
ffff80008111a8c0 d pz5_pins
ffff80008111a8c8 d pz4_pins
ffff80008111a8d0 d pz3_pins
ffff80008111a8d8 d pz2_pins
ffff80008111a8e0 d pz1_pins
ffff80008111a8e8 d pz0_pins
ffff80008111a8f0 d clk_32k_out_py5_pins
ffff80008111a8f8 d pwr_i2c_sda_py4_pins
ffff80008111a900 d pwr_i2c_scl_py3_pins
ffff80008111a908 d lcd_te_py2_pins
ffff80008111a910 d button_home_py1_pins
ffff80008111a918 d button_slide_sw_py0_pins
ffff80008111a920 d button_vol_down_px7_pins
ffff80008111a928 d button_vol_up_px6_pins
ffff80008111a930 d button_power_on_px5_pins
ffff80008111a938 d temp_alert_px4_pins
ffff80008111a940 d als_prox_int_px3_pins
ffff80008111a948 d motion_int_px2_pins
ffff80008111a950 d touch_int_px1_pins
ffff80008111a958 d modem_wake_ap_px0_pins
ffff80008111a960 d touch_clk_pv7_pins
ffff80008111a968 d touch_rst_pv6_pins
ffff80008111a970 d ap_ready_pv5_pins
ffff80008111a978 d lcd_gpio2_pv4_pins
ffff80008111a980 d lcd_gpio1_pv3_pins
ffff80008111a988 d lcd_rst_pv2_pins
ffff80008111a990 d lcd_bl_en_pv1_pins
ffff80008111a998 d lcd_bl_pwm_pv0_pins
ffff80008111a9a0 d uart1_cts_pu3_pins
ffff80008111a9a8 d uart1_rts_pu2_pins
ffff80008111a9b0 d uart1_rx_pu1_pins
ffff80008111a9b8 d uart1_tx_pu0_pins
ffff80008111a9c0 d cam1_strobe_pt1_pins
ffff80008111a9c8 d cam2_pwdn_pt0_pins
ffff80008111a9d0 d cam1_pwdn_ps7_pins
ffff80008111a9d8 d cam_flash_en_ps6_pins
ffff80008111a9e0 d cam_af_en_ps5_pins
ffff80008111a9e8 d cam_rst_ps4_pins
ffff80008111a9f0 d cam_i2c_sda_ps3_pins
ffff80008111a9f8 d cam_i2c_scl_ps2_pins
ffff80008111aa00 d cam2_mclk_ps1_pins
ffff80008111aa08 d cam1_mclk_ps0_pins
ffff80008111aa10 d sdmmc3_dat0_pp5_pins
ffff80008111aa18 d sdmmc3_dat1_pp4_pins
ffff80008111aa20 d sdmmc3_dat2_pp3_pins
ffff80008111aa28 d sdmmc3_dat3_pp2_pins
ffff80008111aa30 d sdmmc3_cmd_pp1_pins
ffff80008111aa38 d sdmmc3_clk_pp0_pins
ffff80008111aa40 d sdmmc1_dat0_pm5_pins
ffff80008111aa48 d sdmmc1_dat1_pm4_pins
ffff80008111aa50 d sdmmc1_dat2_pm3_pins
ffff80008111aa58 d sdmmc1_dat3_pm2_pins
ffff80008111aa60 d sdmmc1_cmd_pm1_pins
ffff80008111aa68 d sdmmc1_clk_pm0_pins
ffff80008111aa70 d pl1_pins
ffff80008111aa78 d pl0_pins
ffff80008111aa80 d pk7_pins
ffff80008111aa88 d pk6_pins
ffff80008111aa90 d pk5_pins
ffff80008111aa98 d pk4_pins
ffff80008111aaa0 d pk3_pins
ffff80008111aaa8 d pk2_pins
ffff80008111aab0 d pk1_pins
ffff80008111aab8 d pk0_pins
ffff80008111aac0 d dap4_sclk_pj7_pins
ffff80008111aac8 d dap4_dout_pj6_pins
ffff80008111aad0 d dap4_din_pj5_pins
ffff80008111aad8 d dap4_fs_pj4_pins
ffff80008111aae0 d gen2_i2c_sda_pj3_pins
ffff80008111aae8 d gen2_i2c_scl_pj2_pins
ffff80008111aaf0 d gen1_i2c_scl_pj1_pins
ffff80008111aaf8 d gen1_i2c_sda_pj0_pins
ffff80008111ab00 d uart4_cts_pi7_pins
ffff80008111ab08 d uart4_rts_pi6_pins
ffff80008111ab10 d uart4_rx_pi5_pins
ffff80008111ab18 d uart4_tx_pi4_pins
ffff80008111ab20 d gps_rst_pi3_pins
ffff80008111ab28 d gps_en_pi2_pins
ffff80008111ab30 d nfc_int_pi1_pins
ffff80008111ab38 d nfc_en_pi0_pins
ffff80008111ab40 d ap_wake_nfc_ph7_pins
ffff80008111ab48 d ph6_pins
ffff80008111ab50 d bt_wake_ap_ph5_pins
ffff80008111ab58 d bt_rst_ph4_pins
ffff80008111ab60 d ap_wake_bt_ph3_pins
ffff80008111ab68 d wifi_wake_ap_ph2_pins
ffff80008111ab70 d wifi_rst_ph1_pins
ffff80008111ab78 d wifi_en_ph0_pins
ffff80008111ab80 d uart2_cts_pg3_pins
ffff80008111ab88 d uart2_rts_pg2_pins
ffff80008111ab90 d uart2_rx_pg1_pins
ffff80008111ab98 d uart2_tx_pg0_pins
ffff80008111aba0 d gen3_i2c_sda_pf1_pins
ffff80008111aba8 d gen3_i2c_scl_pf0_pins
ffff80008111abb0 d pe7_pins
ffff80008111abb8 d pe6_pins
ffff80008111abc0 d dmic3_dat_pe5_pins
ffff80008111abc8 d dmic3_clk_pe4_pins
ffff80008111abd0 d dmic2_dat_pe3_pins
ffff80008111abd8 d dmic2_clk_pe2_pins
ffff80008111abe0 d dmic1_dat_pe1_pins
ffff80008111abe8 d dmic1_clk_pe0_pins
ffff80008111abf0 d uart3_cts_pd4_pins
ffff80008111abf8 d uart3_rts_pd3_pins
ffff80008111ac00 d uart3_rx_pd2_pins
ffff80008111ac08 d uart3_tx_pd1_pins
ffff80008111ac10 d spi4_miso_pd0_pins
ffff80008111ac18 d spi4_mosi_pc7_pins
ffff80008111ac20 d spi4_cs0_pc6_pins
ffff80008111ac28 d spi4_sck_pc5_pins
ffff80008111ac30 d spi1_cs1_pc4_pins
ffff80008111ac38 d spi1_cs0_pc3_pins
ffff80008111ac40 d spi1_sck_pc2_pins
ffff80008111ac48 d spi1_miso_pc1_pins
ffff80008111ac50 d spi1_mosi_pc0_pins
ffff80008111ac58 d spi2_cs0_pb7_pins
ffff80008111ac60 d spi2_sck_pb6_pins
ffff80008111ac68 d spi2_miso_pb5_pins
ffff80008111ac70 d spi2_mosi_pb4_pins
ffff80008111ac78 d dap1_sclk_pb3_pins
ffff80008111ac80 d dap1_dout_pb2_pins
ffff80008111ac88 d dap1_din_pb1_pins
ffff80008111ac90 d dap1_fs_pb0_pins
ffff80008111ac98 d pa6_pins
ffff80008111aca0 d sata_led_active_pa5_pins
ffff80008111aca8 d pex_l1_clkreq_n_pa4_pins
ffff80008111acb0 d pex_l1_rst_n_pa3_pins
ffff80008111acb8 d pex_wake_n_pa2_pins
ffff80008111acc0 d pex_l0_clkreq_n_pa1_pins
ffff80008111acc8 d pex_l0_rst_n_pa0_pins
ffff80008111acd0 d tegra210_pins
ffff80008111bc00 d tegra194_pinctrl_of_match
ffff80008111be58 d tegra194_pinctrl_aon
ffff80008111be98 d tegra194_aon_groups
ffff80008111c718 d tegra194_aon_pins
ffff80008111ca60 d tegra194_pinctrl
ffff80008111caa0 d tegra194_groups
ffff80008111f8e0 d tegra194_functions
ffff80008111fb78 d clk_32k_in_pins
ffff80008111fb80 d soc_pwr_req_pins
ffff80008111fb88 d pmu_int_n_pins
ffff80008111fb90 d shutdown_n_pins
ffff80008111fb98 d qspi_comp_pins
ffff80008111fba0 d eqos_comp_pins
ffff80008111fba8 d sdmmc3_comp_pins
ffff80008111fbb0 d sdmmc1_comp_pins
ffff80008111fbb8 d sdmmc4_dat0_pins
ffff80008111fbc0 d sdmmc4_dat1_pins
ffff80008111fbc8 d sdmmc4_dat2_pins
ffff80008111fbd0 d sdmmc4_dat3_pins
ffff80008111fbd8 d sdmmc4_dat4_pins
ffff80008111fbe0 d sdmmc4_dat5_pins
ffff80008111fbe8 d sdmmc4_dat6_pins
ffff80008111fbf0 d sdmmc4_dat7_pins
ffff80008111fbf8 d sdmmc4_dqs_pins
ffff80008111fc00 d sdmmc4_cmd_pins
ffff80008111fc08 d sdmmc4_clk_pins
ffff80008111fc10 d directdc_comp_pins
ffff80008111fc18 d pex_l5_rst_n_pgg1_pins
ffff80008111fc20 d pex_l5_clkreq_n_pgg0_pins
ffff80008111fc28 d ufs0_rst_pff1_pins
ffff80008111fc30 d ufs0_ref_clk_pff0_pins
ffff80008111fc38 d pwr_i2c_sda_pee6_pins
ffff80008111fc40 d pwr_i2c_scl_pee5_pins
ffff80008111fc48 d power_on_pee4_pins
ffff80008111fc50 d batt_oc_pee3_pins
ffff80008111fc58 d ao_retention_n_pee2_pins
ffff80008111fc60 d vcomp_alert_pee1_pins
ffff80008111fc68 d safe_state_pee0_pins
ffff80008111fc70 d gen8_i2c_sda_pdd2_pins
ffff80008111fc78 d gen8_i2c_scl_pdd1_pins
ffff80008111fc80 d gen2_i2c_sda_pdd0_pins
ffff80008111fc88 d gen2_i2c_scl_pcc7_pins
ffff80008111fc90 d uart3_rx_pcc6_pins
ffff80008111fc98 d uart3_tx_pcc5_pins
ffff80008111fca0 d touch_clk_pcc4_pins
ffff80008111fca8 d spi2_cs0_pcc3_pins
ffff80008111fcb0 d spi2_mosi_pcc2_pins
ffff80008111fcb8 d spi2_miso_pcc1_pins
ffff80008111fcc0 d spi2_sck_pcc0_pins
ffff80008111fcc8 d can1_err_pbb3_pins
ffff80008111fcd0 d can1_wake_pbb2_pins
ffff80008111fcd8 d can1_en_pbb1_pins
ffff80008111fce0 d can1_stb_pbb0_pins
ffff80008111fce8 d can0_err_paa7_pins
ffff80008111fcf0 d can0_wake_paa6_pins
ffff80008111fcf8 d can0_en_paa5_pins
ffff80008111fd00 d can0_stb_paa4_pins
ffff80008111fd08 d can0_din_paa3_pins
ffff80008111fd10 d can0_dout_paa2_pins
ffff80008111fd18 d can1_din_paa1_pins
ffff80008111fd20 d can1_dout_paa0_pins
ffff80008111fd28 d spi1_cs1_pz7_pins
ffff80008111fd30 d spi1_cs0_pz6_pins
ffff80008111fd38 d spi1_mosi_pz5_pins
ffff80008111fd40 d spi1_miso_pz4_pins
ffff80008111fd48 d spi1_sck_pz3_pins
ffff80008111fd50 d usb_vbus_en1_pz2_pins
ffff80008111fd58 d usb_vbus_en0_pz1_pins
ffff80008111fd60 d uart5_cts_pz0_pins
ffff80008111fd68 d uart5_rts_py7_pins
ffff80008111fd70 d uart5_rx_py6_pins
ffff80008111fd78 d uart5_tx_py5_pins
ffff80008111fd80 d spi3_cs1_py4_pins
ffff80008111fd88 d spi3_cs0_py3_pins
ffff80008111fd90 d spi3_mosi_py2_pins
ffff80008111fd98 d spi3_miso_py1_pins
ffff80008111fda0 d spi3_sck_py0_pins
ffff80008111fda8 d uart2_cts_px7_pins
ffff80008111fdb0 d uart2_rts_px6_pins
ffff80008111fdb8 d uart2_rx_px5_pins
ffff80008111fdc0 d uart2_tx_px4_pins
ffff80008111fdc8 d gp_pwm3_px3_pins
ffff80008111fdd0 d gp_pwm2_px2_pins
ffff80008111fdd8 d cv_pwr_req_px1_pins
ffff80008111fde0 d gpu_pwr_req_px0_pins
ffff80008111fde8 d directdc1_out7_pw1_pins
ffff80008111fdf0 d directdc1_out6_pw0_pins
ffff80008111fdf8 d directdc1_out5_pv7_pins
ffff80008111fe00 d directdc1_out4_pv6_pins
ffff80008111fe08 d directdc1_out3_pv5_pins
ffff80008111fe10 d directdc1_out2_pv4_pins
ffff80008111fe18 d directdc1_out1_pv3_pins
ffff80008111fe20 d directdc1_out0_pv2_pins
ffff80008111fe28 d directdc1_in_pv1_pins
ffff80008111fe30 d directdc1_clk_pv0_pins
ffff80008111fe38 d dap5_fs_pu0_pins
ffff80008111fe40 d dap5_din_pt7_pins
ffff80008111fe48 d dap5_dout_pt6_pins
ffff80008111fe50 d dap5_sclk_pt5_pins
ffff80008111fe58 d dap3_fs_pt4_pins
ffff80008111fe60 d dap3_din_pt3_pins
ffff80008111fe68 d dap3_dout_pt2_pins
ffff80008111fe70 d dap3_sclk_pt1_pins
ffff80008111fe78 d soc_gpio33_pt0_pins
ffff80008111fe80 d soc_gpio32_ps7_pins
ffff80008111fe88 d soc_gpio31_ps6_pins
ffff80008111fe90 d soc_gpio30_ps5_pins
ffff80008111fe98 d aud_mclk_ps4_pins
ffff80008111fea0 d dap1_fs_ps3_pins
ffff80008111fea8 d dap1_din_ps2_pins
ffff80008111feb0 d dap1_dout_ps1_pins
ffff80008111feb8 d dap1_sclk_ps0_pins
ffff80008111fec0 d uart1_cts_pr5_pins
ffff80008111fec8 d uart1_rts_pr4_pins
ffff80008111fed0 d uart1_rx_pr3_pins
ffff80008111fed8 d uart1_tx_pr2_pins
ffff80008111fee0 d soc_gpio45_pr1_pins
ffff80008111fee8 d soc_gpio44_pr0_pins
ffff80008111fef0 d soc_gpio43_pq7_pins
ffff80008111fef8 d soc_gpio42_pq6_pins
ffff80008111ff00 d soc_gpio41_pq5_pins
ffff80008111ff08 d soc_gpio40_pq4_pins
ffff80008111ff10 d soc_gpio23_pq3_pins
ffff80008111ff18 d soc_gpio22_pq2_pins
ffff80008111ff20 d soc_gpio21_pq1_pins
ffff80008111ff28 d soc_gpio20_pq0_pins
ffff80008111ff30 d soc_gpio07_pp7_pins
ffff80008111ff38 d soc_gpio06_pp6_pins
ffff80008111ff40 d soc_gpio05_pp5_pins
ffff80008111ff48 d soc_gpio04_pp4_pins
ffff80008111ff50 d cam_i2c_sda_pp3_pins
ffff80008111ff58 d cam_i2c_scl_pp2_pins
ffff80008111ff60 d extperiph2_clk_pp1_pins
ffff80008111ff68 d extperiph1_clk_pp0_pins
ffff80008111ff70 d sdmmc3_dat3_po5_pins
ffff80008111ff78 d sdmmc3_dat2_po4_pins
ffff80008111ff80 d sdmmc3_dat1_po3_pins
ffff80008111ff88 d sdmmc3_dat0_po2_pins
ffff80008111ff90 d sdmmc3_cmd_po1_pins
ffff80008111ff98 d sdmmc3_clk_po0_pins
ffff80008111ffa0 d soc_gpio55_pn2_pins
ffff80008111ffa8 d soc_gpio54_pn1_pins
ffff80008111ffb0 d soc_gpio53_pn0_pins
ffff80008111ffb8 d soc_gpio52_pm7_pins
ffff80008111ffc0 d soc_gpio51_pm6_pins
ffff80008111ffc8 d soc_gpio50_pm5_pins
ffff80008111ffd0 d hdmi_cec_pm4_pins
ffff80008111ffd8 d dp_aux_ch3_hpd_pm3_pins
ffff80008111ffe0 d dp_aux_ch2_hpd_pm2_pins
ffff80008111ffe8 d dp_aux_ch1_hpd_pm1_pins
ffff80008111fff0 d dp_aux_ch0_hpd_pm0_pins
ffff80008111fff8 d sata_dev_slp_pl3_pins
ffff800081120000 d pex_wake_n_pl2_pins
ffff800081120008 d pex_l4_rst_n_pl1_pins
ffff800081120010 d pex_l4_clkreq_n_pl0_pins
ffff800081120018 d pex_l3_rst_n_pk7_pins
ffff800081120020 d pex_l3_clkreq_n_pk6_pins
ffff800081120028 d pex_l2_rst_n_pk5_pins
ffff800081120030 d pex_l2_clkreq_n_pk4_pins
ffff800081120038 d pex_l1_rst_n_pk3_pins
ffff800081120040 d pex_l1_clkreq_n_pk2_pins
ffff800081120048 d pex_l0_rst_n_pk1_pins
ffff800081120050 d pex_l0_clkreq_n_pk0_pins
ffff800081120058 d sdmmc1_dat3_pj5_pins
ffff800081120060 d sdmmc1_dat2_pj4_pins
ffff800081120068 d sdmmc1_dat1_pj3_pins
ffff800081120070 d sdmmc1_dat0_pj2_pins
ffff800081120078 d sdmmc1_cmd_pj1_pins
ffff800081120080 d sdmmc1_clk_pj0_pins
ffff800081120088 d gen1_i2c_sda_pi4_pins
ffff800081120090 d gen1_i2c_scl_pi3_pins
ffff800081120098 d dap2_fs_pi2_pins
ffff8000811200a0 d dap2_din_pi1_pins
ffff8000811200a8 d dap2_dout_pi0_pins
ffff8000811200b0 d dap2_sclk_ph7_pins
ffff8000811200b8 d uart4_cts_ph6_pins
ffff8000811200c0 d uart4_rts_ph5_pins
ffff8000811200c8 d uart4_rx_ph4_pins
ffff8000811200d0 d uart4_tx_ph3_pins
ffff8000811200d8 d soc_gpio14_ph2_pins
ffff8000811200e0 d soc_gpio13_ph1_pins
ffff8000811200e8 d soc_gpio12_ph0_pins
ffff8000811200f0 d soc_gpio11_pg7_pins
ffff8000811200f8 d soc_gpio10_pg6_pins
ffff800081120100 d soc_gpio09_pg5_pins
ffff800081120108 d soc_gpio08_pg4_pins
ffff800081120110 d soc_gpio03_pg3_pins
ffff800081120118 d soc_gpio02_pg2_pins
ffff800081120120 d soc_gpio01_pg1_pins
ffff800081120128 d soc_gpio00_pg0_pins
ffff800081120130 d eqos_sma_mdc_pf5_pins
ffff800081120138 d eqos_sma_mdio_pf4_pins
ffff800081120140 d eqos_rxc_pf3_pins
ffff800081120148 d eqos_rx_ctl_pf2_pins
ffff800081120150 d eqos_rd3_pf1_pins
ffff800081120158 d eqos_rd2_pf0_pins
ffff800081120160 d eqos_rd1_pe7_pins
ffff800081120168 d eqos_rd0_pe6_pins
ffff800081120170 d eqos_tx_ctl_pe5_pins
ffff800081120178 d eqos_td3_pe4_pins
ffff800081120180 d eqos_td2_pe3_pins
ffff800081120188 d eqos_td1_pe2_pins
ffff800081120190 d eqos_td0_pe1_pins
ffff800081120198 d eqos_txc_pe0_pins
ffff8000811201a0 d qspi1_io3_pd3_pins
ffff8000811201a8 d qspi1_io2_pd2_pins
ffff8000811201b0 d qspi1_io1_pd1_pins
ffff8000811201b8 d qspi1_io0_pd0_pins
ffff8000811201c0 d qspi1_cs_n_pc7_pins
ffff8000811201c8 d qspi1_sck_pc6_pins
ffff8000811201d0 d qspi0_io3_pc5_pins
ffff8000811201d8 d qspi0_io2_pc4_pins
ffff8000811201e0 d qspi0_io1_pc3_pins
ffff8000811201e8 d qspi0_io0_pc2_pins
ffff8000811201f0 d qspi0_cs_n_pc1_pins
ffff8000811201f8 d qspi0_sck_pc0_pins
ffff800081120200 d cpu_pwr_req_1_pb1_pins
ffff800081120208 d cpu_pwr_req_0_pb0_pins
ffff800081120210 d dap4_fs_pa7_pins
ffff800081120218 d dap4_din_pa6_pins
ffff800081120220 d dap4_dout_pa5_pins
ffff800081120228 d dap4_sclk_pa4_pins
ffff800081120230 d dap6_fs_pa3_pins
ffff800081120238 d dap6_din_pa2_pins
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ffff80008114de18 d mtk_reset_ops
ffff80008114de38 d mtk_reset_ops_set_clr
ffff80008114de58 D mtk_mux_gate_hwv_fenc_clr_set_upd_ops
ffff80008114df20 D mtk_mux_gate_fenc_clr_set_upd_ops
ffff80008114dfe8 D mtk_mux_gate_clr_set_upd_ops
ffff80008114e0b0 D mtk_mux_clr_set_upd_ops
ffff80008114e178 d fhctl_offset_v1
ffff80008114e1a0 d fhctl_offset_v2
ffff80008114e1c8 d fhctl_ops
ffff80008114e1d8 d __func__.1
ffff80008114e1e8 d __func__.0
ffff80008114e200 d mtk_pllfh_ops
ffff80008114e2c8 d ifr_clks
ffff80008114f288 d __func__.15
ffff80008114f2a0 d plls
ffff80008114f840 d apmixed_clks
ffff80008114fac0 d __func__.17
ffff80008114fae0 d fixed_clks
ffff80008114fb40 d top_divs
ffff800081150720 d top_muxes
ffff800081151260 d top_clks
ffff800081151660 d __func__.16
ffff800081151678 d of_match_clk_mt6765
ffff800081151998 d apmixed_cg_regs
ffff8000811519a8 d ifr5_cg_regs
ffff8000811519b8 d ifr4_cg_regs
ffff8000811519c8 d ifr3_cg_regs
ffff8000811519d8 d ifr2_cg_regs
ffff8000811519e8 d top2_cg_regs
ffff8000811519f8 d top1_cg_regs
ffff800081151a08 d top0_cg_regs
ffff800081151a18 d camtm_parents
ffff800081151a38 d ulposc_parents
ffff800081151a60 d aes_fde_parents
ffff800081151a90 d seninf_parents
ffff800081151ab0 d pwm_parents
ffff800081151ac8 d i2c_parents
ffff800081151af0 d spm_parents
ffff800081151b00 d usb_top_parents
ffff800081151b10 d dxcc_parents
ffff800081151b30 d sspm_parents
ffff800081151b48 d disp_pwm_parents
ffff800081151b68 d aud_engen1_parents
ffff800081151b88 d aud_1_parents
ffff800081151b98 d aud_intbus_parents
ffff800081151bb0 d audio_parents
ffff800081151bd0 d msdc30_1_parents
ffff800081151c10 d msdc50_0_parents
ffff800081151c50 d msdc5hclk_parents
ffff800081151c70 d spi_parents
ffff800081151c90 d uart_parents
ffff800081151ca0 d camtg_parents
ffff800081151cd8 d atb_parents
ffff800081151cf0 d mfg_parents
ffff800081151d10 d scp_parents
ffff800081151d48 d mm_parents
ffff800081151d88 d mem_parents
ffff800081151da0 d axi_parents
ffff800081151dc0 d top_fixed_clks
ffff800081151de0 d top_divs
ffff800081152ab0 d top_aud_muxes
ffff800081152c00 d plls
ffff8000811532c0 d apmixed_clks
ffff800081153580 d of_match_clk_mt6779_infra
ffff800081153710 d infra_desc
ffff800081153798 d of_match_clk_mt6779
ffff8000811539f0 d apmixed_cg_regs
ffff800081153a00 d infra_clks
ffff8000811554c0 d infra3_cg_regs
ffff8000811554d0 d infra2_cg_regs
ffff8000811554e0 d infra1_cg_regs
ffff8000811554f0 d infra0_cg_regs
ffff800081155500 d i2s5_m_ck_parents
ffff800081155510 d i2s4_m_ck_parents
ffff800081155520 d i2s3_m_ck_parents
ffff800081155530 d i2s2_m_ck_parents
ffff800081155540 d i2s1_m_ck_parents
ffff800081155550 d i2s0_m_ck_parents
ffff800081155560 d top_muxes
ffff8000811569a0 d camtg5_parents
ffff8000811569e0 d audio_h_parents
ffff800081156a00 d pwm_parents
ffff800081156a10 d camtm_parents
ffff800081156a30 d vdec_parents
ffff800081156a88 d venc_parents
ffff800081156af0 d dpmaif_parents
ffff800081156b20 d adsp_parents
ffff800081156b58 d aud_2_parents
ffff800081156b68 d aud_1_parents
ffff800081156b78 d fufs_parents
ffff800081156b98 d faes_ufsfde_parents
ffff800081156bc8 d aud_engen2_parents
ffff800081156be8 d aud_engen1_parents
ffff800081156c08 d dxcc_parents
ffff800081156c28 d seninf2_parents
ffff800081156c68 d seninf1_parents
ffff800081156ca8 d seninf_parents
ffff800081156ce8 d i2c_parents
ffff800081156d00 d spm_parents
ffff800081156d18 d ssusb_top_xhci_parents
ffff800081156d38 d usb_top_parents
ffff800081156d58 d disppwm_parents
ffff800081156d80 d scam_parents
ffff800081156d90 d dpi0_parents
ffff800081156db8 d sspm_parents
ffff800081156de0 d atb_parents
ffff800081156df8 d fpwrap_ulposc_parents
ffff800081156e20 d aud_intbus_parents
ffff800081156e38 d audio_parents
ffff800081156e58 d msdc30_1_parents
ffff800081156e80 d msdc50_0_parents
ffff800081156eb0 d msdc50_hclk_parents
ffff800081156ec8 d spi_parents
ffff800081156ee8 d uart_parents
ffff800081156ef8 d camtg4_parents
ffff800081156f38 d camtg3_parents
ffff800081156f78 d camtg2_parents
ffff800081156fb8 d camtg_parents
ffff800081156ff8 d f52m_mfg_parents
ffff800081157018 d mfg_parents
ffff800081157038 d ipu_if_parents
ffff8000811570b8 d dsp3_parents
ffff800081157138 d dsp2_parents
ffff8000811571b8 d dsp1_parents
ffff800081157238 d dsp_parents
ffff8000811572b8 d ccu_parents
ffff800081157308 d cam_parents
ffff800081157358 d dpe_parents
ffff800081157398 d ipe_parents
ffff8000811573d8 d img_parents
ffff800081157418 d scp_parents
ffff800081157458 d mm_parents
ffff800081157488 d axi_parents
ffff8000811574a8 d plls
ffff800081157ad8 d __func__.16
ffff800081157af8 d of_match_clk_mt6795_apmixed
ffff800081157c88 d cpu_muxes
ffff800081157cf8 d infra_gates
ffff800081158078 d clk_rst_desc
ffff8000811580a0 d of_match_clk_mt6795_infracfg
ffff800081158230 d ca53_c1_parents
ffff800081158250 d ca53_c0_parents
ffff800081158270 d infra_cg_regs
ffff800081158280 d peri_clks
ffff800081158360 d peri_gates
ffff800081158ae0 d clk_rst_desc
ffff800081158b08 d of_match_clk_mt6795_pericfg
ffff800081158c98 d uart_ck_sel_parents
ffff800081158ca8 d peri_cg_regs
ffff800081158cb8 d of_match_clk_mt6795_topckgen
ffff800081158e48 d topck_desc
ffff800081158ed0 d top_muxes
ffff800081159a70 d top_divs
ffff80008115a600 d fixed_clks
ffff80008115a6a0 d venc_parents
ffff80008115a6f0 d vdec_parents
ffff80008115a740 d usb30_parents
ffff80008115a760 d usb20_parents
ffff80008115a778 d uart_parents
ffff80008115a788 d spi_parents
ffff80008115a7c0 d scp_parents
ffff80008115a7f0 d scam_parents
ffff80008115a810 d pwm_parents
ffff80008115a830 d pmicspi_parents
ffff80008115a870 d msdc30_3_parents
ffff80008115a8b0 d msdc30_2_parents
ffff80008115a8f0 d msdc30_1_parents
ffff80008115a930 d msdc50_0_parents
ffff80008115a990 d msdc50_0_h_parents
ffff80008115a9c0 d mjc_parents
ffff80008115aa20 d mm_parents
ffff80008115aa68 d mfg_parents
ffff80008115aae8 d mem_parents
ffff80008115aaf8 d mem_mfg_in_parents
ffff80008115ab10 d irda_parents
ffff80008115ab30 d i2s3_b_ck_parents
ffff80008115ab40 d i2s3_m_ck_parents
ffff80008115ab50 d i2s2_m_ck_parents
ffff80008115ab60 d i2s1_m_ck_parents
ffff80008115ab70 d i2s0_m_ck_parents
ffff80008115ab80 d dpi0_parents
ffff80008115abb8 d ddrphycfg_parents
ffff80008115abc8 d cci400_parents
ffff80008115ac08 d camtg_parents
ffff80008115ac40 d axi_parents
ffff80008115ac80 d axi_mfg_in_parents
ffff80008115ac98 d audio_parents
ffff80008115acb8 d aud_intbus_parents
ffff80008115acf0 d aud_2_parents
ffff80008115ad10 d aud_1_parents
ffff80008115ad30 d of_match_clk_mt6795_mfg
ffff80008115aec0 d mfg_desc
ffff80008115af48 d mfg_clks
ffff80008115b048 d mfg_cg_regs
ffff80008115b058 d clk_mt6795_mm_id_table
ffff80008115b098 d mm_desc
ffff80008115b120 d mm_gates
ffff80008115bba0 d mm1_cg_regs
ffff80008115bbb0 d mm0_cg_regs
ffff80008115bbc0 d of_match_clk_mt6795_vdecsys
ffff80008115bd50 d vdec_desc
ffff80008115bdd8 d vdec_clks
ffff80008115be58 d vdec1_cg_regs
ffff80008115be68 d vdec0_cg_regs
ffff80008115be78 d of_match_clk_mt6795_vencsys
ffff80008115c008 d venc_desc
ffff80008115c090 d venc_clks
ffff80008115c190 d venc_cg_regs
ffff80008115c1a0 d plls
ffff80008115c740 d infra_fixed_divs
ffff80008115c768 d top_fixed_divs
ffff80008115d0c8 d top_muxes
ffff80008115d800 d __func__.15
ffff80008115d818 d of_match_clk_mt6797
ffff80008115db38 d infra_clks
ffff80008115eff8 d infra2_cg_regs
ffff80008115f008 d infra1_cg_regs
ffff80008115f018 d infra0_cg_regs
ffff80008115f028 d anc_md32_parents
ffff80008115f040 d mfg_52m_parents
ffff80008115f060 d audio_h_parents
ffff80008115f080 d bsi_spi_parents
ffff80008115f0a0 d spm_parents
ffff80008115f0b0 d ssusb_top_sys_parents
ffff80008115f0c0 d aud_2_parents
ffff80008115f0d0 d aud_1_parents
ffff80008115f0e0 d dpi0_parents
ffff80008115f118 d mjc_parents
ffff80008115f138 d atb_parents
ffff80008115f150 d scp_parents
ffff80008115f170 d pmicspi_parents
ffff80008115f1a8 d aud_intbus_parents
ffff80008115f1c0 d audio_parents
ffff80008115f1e0 d msdc30_2_parents
ffff80008115f218 d msdc30_1_parents
ffff80008115f250 d msdc50_0_parents
ffff80008115f298 d msdc50_0_hclk_parents
ffff80008115f2b8 d usb20_parents
ffff80008115f2d0 d ulposc_spi_ck_mux_parents
ffff80008115f2e0 d spi_parents
ffff80008115f300 d uart_parents
ffff80008115f310 d camtg
ffff80008115f328 d mfg_parents
ffff80008115f348 d venc_parents
ffff80008115f360 d vdec_parents
ffff80008115f398 d pwm_parents
ffff80008115f3d0 d mm_parents
ffff80008115f3f0 d ddrphycfg_parents
ffff80008115f410 d ulposc_axi_ck_mux_pre_parents
ffff80008115f420 d ulposc_axi_ck_mux_parents
ffff80008115f430 d axi_parents
ffff80008115f448 d plls
ffff80008115f8c8 d __func__.15
ffff80008115f8e8 d of_match_clk_mt7981_apmixed
ffff80008115fa78 d of_match_clk_mt7981_topckgen
ffff80008115fc08 d topck_desc
ffff80008115fc90 d top_muxes
ffff8000811608f0 d top_divs
ffff8000811614d0 d of_match_clk_mt7981_infracfg
ffff800081161660 d infracfg_desc
ffff8000811616e8 d infra_clks
ffff800081162328 d infra2_cg_regs
ffff800081162338 d infra1_cg_regs
ffff800081162348 d infra0_cg_regs
ffff800081162358 d infra_muxes
ffff800081162778 d infra_divs
ffff8000811627a0 d of_match_clk_mt7981_eth
ffff800081162ac0 d sgmii1_desc
ffff800081162b48 d sgmii0_desc
ffff800081162bd0 d eth_desc
ffff800081162c58 d eth_clks
ffff800081162d58 d eth_cg_regs
ffff800081162d68 d sgmii1_clks
ffff800081162e68 d sgmii1_cg_regs
ffff800081162e78 d sgmii0_clks
ffff800081162f78 d sgmii0_cg_regs
ffff800081162f88 d plls
ffff800081163408 d __func__.15
ffff800081163428 d of_match_clk_mt7986_apmixed
ffff8000811635b8 d of_match_clk_mt7986_topckgen
ffff800081163748 d topck_desc
ffff8000811637d0 d top_muxes
ffff8000811645b0 d top_divs
ffff800081164998 d top_fixed_clks
ffff8000811649d8 d of_match_clk_mt7986_infracfg
ffff800081164b68 d infra_desc
ffff800081164bf0 d infra_clks
ffff800081165770 d infra2_cg_regs
ffff800081165780 d infra1_cg_regs
ffff800081165790 d infra0_cg_regs
ffff8000811657a0 d infra_muxes
ffff800081165b00 d infra_divs
ffff800081165b28 d of_match_clk_mt7986_eth
ffff800081165e48 d sgmii1_desc
ffff800081165ed0 d sgmii0_desc
ffff800081165f58 d eth_desc
ffff800081165fe0 d eth_clks
ffff800081166120 d eth_cg_regs
ffff800081166130 d sgmii1_clks
ffff800081166230 d sgmii1_cg_regs
ffff800081166240 d sgmii0_clks
ffff800081166340 d sgmii0_cg_regs
ffff800081166350 d plls
ffff800081166a10 d of_match_clk_mt7988_apmixed
ffff800081166ba0 d of_match_clk_mt7988_topckgen
ffff800081166df8 d mcusys_desc
ffff800081166e80 d mcu_arm_div_parents
ffff800081166e98 d mcu_bus_div_parents
ffff800081166eb0 d topck_desc
ffff800081166f38 d top_aud_divs
ffff800081166f70 d top_muxes
ffff800081168b30 d eth_mii_parents
ffff800081168b40 d netsys_tops_400m_parents
ffff800081168b50 d macsec_parents
ffff800081168b68 d mcusys_backup_625m_parents
ffff800081168b78 d da_xtp_glb_p0_parents
ffff800081168b88 d dramc_md32_parents
ffff800081168ba0 d npu_tops_parents
ffff800081168bb0 d bus_tops_parents
ffff800081168bc8 d eth_xgmii_parents
ffff800081168be0 d eth_sys_200m_parents
ffff800081168bf0 d eth_refck_50m_parents
ffff800081168c00 d sysapb_parents
ffff800081168c10 d sgm_0_parents
ffff800081168c20 d usxgmii_sbus_0_parents
ffff800081168c30 d sspxtp_parents
ffff800081168c40 d aud_l_parents
ffff800081168c58 d a1sys_parents
ffff800081168c68 d aud_parents
ffff800081168c78 d usb_frmcnt_parents
ffff800081168c88 d pextp_tl_ck_parents
ffff800081168cb0 d pcie_mbist_250m_parents
ffff800081168cc0 d i2c_parents
ffff800081168ce0 d pwm_parents
ffff800081168d10 d spinfi_parents
ffff800081168d50 d nfi1x_parents
ffff800081168d90 d spi_parents
ffff800081168dd0 d emmc_400m_parents
ffff800081168e00 d emmc_250m_parents
ffff800081168e18 d uart_parents
ffff800081168e30 d axi_infra_parents
ffff800081168e40 d eip197_parents
ffff800081168e70 d netsys_mcu_parents
ffff800081168ea0 d eth_gmii_parents
ffff800081168eb0 d netsys_gsw_parents
ffff800081168ec8 d netsys_2x_parents
ffff800081168ee0 d netsys_500m_parents
ffff800081168ef8 d netsys_parents
ffff800081168f10 d top_divs
ffff800081169398 d top_fixed_clks
ffff8000811693b8 d of_match_clk_mt7988_infracfg
ffff800081169548 d infra_desc
ffff8000811695d0 d infra_clks
ffff80008116a9d0 d infra3_cg_regs
ffff80008116a9e0 d infra2_cg_regs
ffff80008116a9f0 d infra1_cg_regs
ffff80008116aa00 d infra0_cg_regs
ffff80008116aa10 d infra_muxes
ffff80008116b130 d of_match_clk_mt7988_eth
ffff80008116b518 d ethwarp_desc
ffff80008116b5a0 d ethwarp_rst_desc
ffff80008116b5c8 d ethwarp_clks
ffff80008116b688 d ethwarp_cg_regs
ffff80008116b698 d sgmii1_desc
ffff80008116b720 d sgmii1_clks
ffff80008116b7a0 d sgmii0_desc
ffff80008116b828 d sgmii0_clks
ffff80008116b8a8 d sgmii_cg_regs
ffff80008116b8b8 d ethdma_desc
ffff80008116b940 d ethdma_clks
ffff80008116bb80 d ethdma_cg_regs
ffff80008116bb90 d of_match_clk_mt7988_xfipll
ffff80008116bd20 d xfipll_desc
ffff80008116bda8 d xfipll_clks
ffff80008116bde8 d xfipll_divs
ffff80008116be10 d xfipll_cg_regs
ffff80008116be20 d plls
ffff80008116c2a0 d adj_divs
ffff80008116c2d0 d of_match_clk_mt8167_apmixed
ffff80008116c460 d mmpll_div_table
ffff80008116c4c0 d of_match_clk_mt8167
ffff80008116c718 d infra_desc
ffff80008116c7a0 d topck_desc
ffff80008116c828 d top_clks
ffff80008116e1a8 d top5_cg_regs
ffff80008116e1b8 d top4_cg_regs
ffff80008116e1c8 d top3_cg_regs
ffff80008116e1d8 d top2_cg_regs
ffff80008116e1e8 d top1_cg_regs
ffff80008116e1f8 d top0_cg_regs
ffff80008116e208 d top_adj_divs
ffff80008116e3b8 d ifr_muxes
ffff80008116e4d0 d ifr_i2c0_parents
ffff80008116e4e0 d ifr_eth_25m_parents
ffff80008116e4f0 d ifr_mux1_parents
ffff80008116e510 d nfiecc_parents
ffff80008116e538 d csw_nfiecc_parents
ffff80008116e560 d dbg_atclk_parents
ffff80008116e588 d bsi_parents
ffff80008116e5a8 d uart2_parents
ffff80008116e5b8 d aud_spdifin_parents
ffff80008116e5c8 d spi_parents
ffff80008116e5e8 d pwm_parents
ffff80008116e5f8 d aud_i2s0_m_parents
ffff80008116e608 d i2c_parents
ffff80008116e628 d aud_engen2_parents
ffff80008116e648 d aud_engen1_parents
ffff80008116e668 d aud2_parents
ffff80008116e678 d aud1_parents
ffff80008116e688 d slow_mfg_parents
ffff80008116e6a0 d axi_mfg_in_parents
ffff80008116e6c0 d dpi1_mm_parents
ffff80008116e6e8 d dpi0_mm_parents
ffff80008116e710 d vdec_mm_parents
ffff80008116e740 d eth_parents
ffff80008116e768 d msdc2_parents
ffff80008116e7a8 d spinor_parents
ffff80008116e7e8 d scam_mm_parents
ffff80008116e810 d usb_78m_parents
ffff80008116e838 d smi_mm_parents
ffff80008116e8a0 d ddrphycfg_parents
ffff80008116e8b0 d mfg_mm_parents
ffff80008116e9d8 d nfi1x_pad_parents
ffff80008116e9e8 d nfi2x_pad_parents
ffff80008116ec90 d aud_intbus_parents
ffff80008116ecb8 d qaxi_aud26m_parents
ffff80008116ecc8 d pmicspi_parents
ffff80008116ece8 d spm_52m_parents
ffff80008116ecf8 d msdc1_parents
ffff80008116ed38 d uart1_parents
ffff80008116ed48 d pwm_mm_parents
ffff80008116ed58 d camtg_mm_parents
ffff80008116ed80 d msdc0_parents
ffff80008116edc0 d csw_mux_mfg_parents
ffff80008116ee00 d ahb_infra_parents
ffff80008116ee68 d emi_ddrphy_parents
ffff80008116ee78 d gfmux_emi1x_parents
ffff80008116ee88 d uart0_parents
ffff80008116ee98 d top_divs
ffff80008116f6e0 d fixed_clks
ffff80008116f7a0 d of_match_clk_mt8167_audsys
ffff80008116f930 d aud_desc
ffff80008116f9b8 d aud_clks
ffff80008116fcf8 d aud_cg_regs
ffff80008116fd08 d of_match_clk_mt8167_imgsys
ffff80008116fe98 d img_desc
ffff80008116ff20 d img_clks
ffff8000811700a0 d img_cg_regs
ffff8000811700b0 d of_match_clk_mt8167_mfgcfg
ffff800081170240 d mfg_desc
ffff8000811702c8 d mfg_clks
ffff8000811703c8 d mfg_cg_regs
ffff8000811703d8 d clk_mt8167_mm_id_table
ffff800081170418 d mm_desc
ffff8000811704a0 d mm_clks
ffff800081170d20 d mm1_cg_regs
ffff800081170d30 d mm0_cg_regs
ffff800081170d40 d of_match_clk_mt8167_vdec
ffff800081170ed0 d vdec_desc
ffff800081170f58 d vdec_clks
ffff800081170fd8 d vdec1_cg_regs
ffff800081170fe8 d vdec0_cg_regs
ffff800081170ff8 d plls
ffff800081171628 d apmixed_clks
ffff8000811718e8 d of_match_clk_mt8183_apmixed
ffff800081171a78 d mfgpll_div_table
ffff800081171ad8 d armpll_div_table
ffff800081171b38 d apmixed_cg_regs
ffff800081171b50 d top_muxes
ffff800081172b10 d of_match_clk_mt8183
ffff800081172ef8 d topck_desc
ffff800081172f80 d peri_desc
ffff800081173008 d mcu_desc
ffff800081173090 d infra_desc
ffff800081173118 d clk_rst_desc
ffff800081173140 d peri_clks
ffff800081173180 d peri_cg_regs
ffff800081173190 d infra_clks
ffff800081174ad0 d infra3_cg_regs
ffff800081174ae0 d infra2_cg_regs
ffff800081174af0 d infra1_cg_regs
ffff800081174b00 d infra0_cg_regs
ffff800081174b10 d top_clks
ffff800081174b90 d top_cg_regs
ffff800081174ba0 d mcu_bus_parents
ffff800081174bc0 d mcu_mp2_parents
ffff800081174be0 d mcu_mp0_parents
ffff800081174c00 d apll_i2s5_parents
ffff800081174c10 d apll_i2s4_parents
ffff800081174c20 d apll_i2s3_parents
ffff800081174c30 d apll_i2s2_parents
ffff800081174c40 d apll_i2s1_parents
ffff800081174c50 d apll_i2s0_parents
ffff800081174c60 d aud_2_parents
ffff800081174c70 d aud_1_parents
ffff800081174c80 d fufs_parents
ffff800081174ca0 d faes_ufsfde_parents
ffff800081174cd0 d aud_engen2_parents
ffff800081174cf0 d aud_engen1_parents
ffff800081174d10 d dxcc_parents
ffff800081174d30 d seninf_parents
ffff800081174d50 d scp_parents
ffff800081174d88 d i2c_parents
ffff800081174da0 d spm_parents
ffff800081174db0 d ssusb_top_xhci_parents
ffff800081174dd0 d usb_top_parents
ffff800081174df0 d disppwm_parents
ffff800081174e18 d scam_parents
ffff800081174e28 d dpi0_parents
ffff800081174e70 d sspm_parents
ffff800081174e98 d atb_parents
ffff800081174eb0 d fpwrap_ulposc_parents
ffff800081174ed0 d pmicspi_parents
ffff800081174ee8 d aud_intbus_parents
ffff800081174f00 d audio_parents
ffff800081174f20 d msdc30_2_parents
ffff800081174f48 d msdc30_1_parents
ffff800081174f70 d msdc50_0_parents
ffff800081174fa0 d msdc50_hclk_parents
ffff800081174fb8 d spi_parents
ffff800081174fd8 d uart_parents
ffff800081174fe8 d camtg4_parents
ffff800081175028 d camtg3_parents
ffff800081175068 d camtg2_parents
ffff8000811750a8 d camtg_parents
ffff8000811750e8 d f52m_mfg_parents
ffff800081175108 d mfg_parents
ffff800081175128 d ipu_if_parents
ffff800081175170 d dsp2_parents
ffff8000811751b8 d dsp1_parents
ffff800081175200 d dsp_parents
ffff800081175248 d cam_parents
ffff800081175298 d img_parents
ffff8000811752d8 d mm_parents
ffff800081175308 d axi_parents
ffff800081175328 d top_divs
ffff800081175e90 d top_fixed_clks
ffff800081175ef0 d plls
ffff8000811766d0 d of_match_clk_mt8186_apmixed
ffff800081176860 d of_match_clk_mt8186_topck
ffff8000811769f0 d topck_desc
ffff800081176a80 d top_mtk_muxes
ffff800081178220 d apll_mck_parents
ffff800081178230 d adsp_bus_parents
ffff800081178268 d u3_occ_500m_parents
ffff800081178278 d u3_occ_250m_parents
ffff800081178288 d dpi_parents
ffff8000811782c0 d wpe_parents
ffff800081178308 d ssusb_parents
ffff800081178320 d nna2_parents
ffff8000811783a0 d nna_parents
ffff800081178420 d spinor_parents
ffff800081178450 d spmi_mst_parents
ffff800081178488 d dsi_occ_parents
ffff8000811784a8 d dvfsrc_parents
ffff8000811784b8 d audiodsp_parents
ffff8000811784e8 d aes_fde_parents
ffff800081178508 d ufs_parents
ffff800081178528 d audio_h_parents
ffff800081178548 d mdp_parents
ffff800081178590 d disp_parents
ffff8000811785d8 d vdec_parents
ffff800081178610 d dpmaif_parents
ffff800081178638 d isp_parents
ffff800081178680 d venc_parents
ffff8000811786c0 d camtm_parents
ffff8000811786d8 d pwrap_ulposc_parents
ffff800081178710 d aes_msdcfde_parents
ffff800081178740 d seninf_parents
ffff800081178760 d pwm_parents
ffff800081178780 d i2c_parents
ffff8000811787a0 d spm_parents
ffff8000811787c0 d srck_parents
ffff8000811787d8 d usb_parents
ffff8000811787f0 d dxcc_parents
ffff800081178808 d sspm_parents
ffff800081178830 d disp_pwm_parents
ffff800081178858 d aud_engen2_parents
ffff800081178878 d aud_engen1_parents
ffff800081178898 d aud_2_parents
ffff8000811788a8 d aud_1_parents
ffff8000811788b8 d aud_intbus_parents
ffff8000811788d0 d audio_parents
ffff8000811788f0 d msdc30_1_parents
ffff800081178918 d msdc50_0_parents
ffff800081178950 d msdc5hclk_parents
ffff800081178970 d spi_parents
ffff8000811789b0 d uart_parents
ffff8000811789c0 d camtg_parents
ffff8000811789f8 d mfg_parents
ffff800081178a18 d scp_parents
ffff800081178a48 d axi_parents
ffff800081178a68 d top_divs
ffff8000811793c8 d top_fixed_clks
ffff800081179428 d of_match_clk_mt8186_infra_ao
ffff8000811795b8 d infra_ao_desc
ffff800081179640 d infra_ao_clks
ffff80008117af80 d infra_ao3_cg_regs
ffff80008117af90 d infra_ao2_cg_regs
ffff80008117afa0 d infra_ao1_cg_regs
ffff80008117afb0 d infra_ao0_cg_regs
ffff80008117afc0 d of_match_clk_mt8186_cam
ffff80008117b2e0 d cam_rawb_desc
ffff80008117b368 d cam_rawa_desc
ffff80008117b3f0 d cam_desc
ffff80008117b478 d cam_rawb_clks
ffff80008117b538 d cam_rawa_clks
ffff80008117b5f8 d cam_clks
ffff80008117b9b8 d cam_cg_regs
ffff80008117b9c8 d of_match_clk_mt8186_img
ffff80008117bc20 d img2_desc
ffff80008117bca8 d img1_desc
ffff80008117bd30 d img2_clks
ffff80008117beb0 d img1_clks
ffff80008117bfb0 d img_cg_regs
ffff80008117bfc0 d of_match_clk_mt8186_imp_iic_wrap
ffff80008117c150 d imp_iic_wrap_desc
ffff80008117c1d8 d imp_iic_wrap_clks
ffff80008117c458 d imp_iic_wrap_cg_regs
ffff80008117c468 d of_match_clk_mt8186_ipe
ffff80008117c5f8 d ipe_desc
ffff80008117c680 d ipe_clks
ffff80008117c880 d ipe_cg_regs
ffff80008117c890 d of_match_clk_mt8186_mcu
ffff80008117ca20 d mcu_desc
ffff80008117caa8 d mcu_armpll_bus_parents
ffff80008117cac8 d mcu_armpll_bl_parents
ffff80008117cae8 d mcu_armpll_ll_parents
ffff80008117cb08 d of_match_clk_mt8186_mdp
ffff80008117cc98 d mdp_desc
ffff80008117cd20 d mdp_clks
ffff80008117d2a0 d mdp2_cg_regs
ffff80008117d2b0 d mdp0_cg_regs
ffff80008117d2c0 d of_match_clk_mt8186_mfg
ffff80008117d450 d mfg_desc
ffff80008117d4d8 d mfg_clks
ffff80008117d518 d mfg_cg_regs
ffff80008117d528 d clk_mt8186_mm_id_table
ffff80008117d568 d mm_desc
ffff80008117d5f0 d mm_clks
ffff80008117dc30 d mm1_cg_regs
ffff80008117dc40 d mm0_cg_regs
ffff80008117dc50 d of_match_clk_mt8186_vdec
ffff80008117dde0 d vdec_desc
ffff80008117de68 d vdec_clks
ffff80008117e068 d vdec3_cg_regs
ffff80008117e078 d vdec2_cg_regs
ffff80008117e088 d vdec1_cg_regs
ffff80008117e098 d vdec0_cg_regs
ffff80008117e0a8 d of_match_clk_mt8186_venc
ffff80008117e238 d venc_desc
ffff80008117e2c0 d venc_clks
ffff80008117e3c0 d venc_cg_regs
ffff80008117e3d0 d of_match_clk_mt8186_wpe
ffff80008117e560 d wpe_desc
ffff80008117e5e8 d wpe_clks
ffff80008117e6e8 d wpe_cg_regs
ffff80008117e6f8 d apmixed_clks
ffff80008117e738 d plls
ffff80008117efa8 d of_match_clk_mt8188_apmixed
ffff80008117f138 d apmixed_cg_regs
ffff80008117f148 d top_clks
ffff80008117f648 d top_adj_divs
ffff80008117f798 d top_divs
ffff8000811803c8 d top_fixed_clks
ffff800081180488 d mfg_fast_ref_parents
ffff800081180498 d of_match_clk_mt8188_topck
ffff800081180628 d top1_cg_regs
ffff800081180638 d top0_cg_regs
ffff800081180648 d top_mtk_muxes
ffff800081182868 d srck_parents
ffff800081182878 d ulposc_parents
ffff800081182898 d spinor_parents
ffff8000811828b8 d ecc_parents
ffff8000811828e8 d a4sys_parents
ffff800081182908 d a3sys_parents
ffff800081182928 d a2sys_parents
ffff800081182938 d a1sys_hp_parents
ffff800081182948 d aud_iec_parents
ffff800081182978 d dptx_parents
ffff8000811829a8 d i2si2_parents
ffff8000811829d8 d i2si1_parents
ffff800081182a08 d i2so2_parents
ffff800081182a38 d i2so1_parents
ffff800081182a68 d apll5_parents
ffff800081182a78 d apll4_parents
ffff800081182a88 d apll3_parents
ffff800081182a98 d apll2_parents
ffff800081182aa8 d apll1_parents
ffff800081182ab8 d asm_l_parents
ffff800081182ad8 d asm_h_parents
ffff800081182af8 d audio_local_bus_parents
ffff800081182b58 d adsp_parents
ffff800081182bb8 d snps_eth_50m_rmii_parents
ffff800081182bc8 d snps_eth_62p4m_ptp_parents
ffff800081182be8 d snps_eth_250m_parents
ffff800081182bf8 d hdmi_apb_parents
ffff800081182c10 d hdcp_24m_parents
ffff800081182c30 d hdcp_parents
ffff800081182c50 d wpe_vpp_parents
ffff800081182cc8 d dsi_occ_parents
ffff800081182ce8 d aes_msdcfde_parents
ffff800081182d18 d tl_parents
ffff800081182d30 d dvfsrc_parents
ffff800081182d50 d spmi_m_mst_parents
ffff800081182da0 d spmi_p_mst_parents
ffff800081182df0 d mcupm_parents
ffff800081182e08 d pwm_parents
ffff800081182e28 d vdec_parents
ffff800081182ea8 d venc_parents
ffff800081182f28 d gcpu_parents
ffff800081182f50 d seninf1_parents
ffff800081182f90 d seninf_parents
ffff800081182fd0 d i2c_parents
ffff800081182fe8 d ssusb_xhci_3p_parents
ffff800081183008 d usb_3p_parents
ffff800081183028 d ssusb_xhci_2p_parents
ffff800081183048 d usb_2p_parents
ffff800081183068 d ssusb_xhci_parents
ffff800081183088 d usb_parents
ffff8000811830a8 d disp_pwm1_parents
ffff8000811830d0 d disp_pwm0_parents
ffff800081183100 d dpi_parents
ffff800081183148 d edp_parents_idx
ffff800081183150 d edp_parents
ffff800081183178 d dp_parents_idx
ffff800081183180 d dp_parents
ffff8000811831a8 d sspm_parents
ffff8000811831d8 d atb_parents
ffff8000811831f0 d pwrap_ulposc_parents
ffff800081183230 d audio_h_parents
ffff800081183250 d aud_intbus_parents
ffff800081183268 d intdir_parents
ffff800081183288 d msdc30_2_parents
ffff8000811832b0 d msdc30_1_parents
ffff8000811832d8 d msdc50_0_parents
ffff800081183308 d msdc5hclk_parents
ffff800081183320 d spi_parents
ffff800081183360 d uart_parents
ffff800081183370 d camtg3_parents
ffff8000811833b0 d camtg2_parents
ffff8000811833f0 d camtg_parents
ffff800081183430 d mfg_core_tmp_parents
ffff800081183440 d dsp7_parents
ffff800081183480 d dsp6_parents
ffff8000811834c0 d dsp5_parents
ffff800081183500 d dsp4_parents
ffff800081183540 d dsp3_parents
ffff800081183580 d dsp2_parents
ffff8000811835c0 d dsp1_parents
ffff800081183600 d dsp_parents
ffff800081183640 d camtm_parents
ffff800081183660 d img_parents
ffff8000811836c8 d ccu_ahb_parents
ffff800081183718 d ccu_parents
ffff800081183768 d cam_parents
ffff8000811837c0 d ipe_parents
ffff800081183820 d ethdr_parents
ffff800081183898 d vpp_parents
ffff800081183910 d bus_aximem_parents
ffff800081183938 d scp_parents
ffff800081183978 d spm_parents
ffff800081183998 d axi_parents
ffff8000811839d0 d of_match_clk_mt8188_peri_ao
ffff800081183b60 d peri_ao_desc
ffff800081183be8 d peri_ao_clks
ffff800081183f28 d peri_ao_cg_regs
ffff800081183f38 d of_match_clk_mt8188_infra_ao
ffff8000811840c8 d infra_ao_desc
ffff800081184150 d infra_ao_rst_desc
ffff800081184178 d infra_ao_clks
ffff8000811854f8 d infra_ao4_cg_regs
ffff800081185508 d infra_ao3_cg_regs
ffff800081185518 d infra_ao2_cg_regs
ffff800081185528 d infra_ao1_cg_regs
ffff800081185538 d infra_ao0_cg_regs
ffff800081185548 d of_match_clk_mt8188_adsp_audio26m
ffff8000811856d8 d adsp_audio26m_desc
ffff800081185760 d adsp_audio26m_clks
ffff8000811857a0 d adsp_audio26m_cg_regs
ffff8000811857b0 d of_match_clk_mt8188_cam
ffff800081185c60 d cam_yuvb_desc
ffff800081185ce8 d cam_yuva_desc
ffff800081185d70 d cam_rawb_desc
ffff800081185df8 d cam_rawa_desc
ffff800081185e80 d cam_main_desc
ffff800081185f08 d cam_sys_rst_desc
ffff800081185f30 d cam_yuvb_clks
ffff800081185ff0 d cam_yuva_clks
ffff8000811860b0 d cam_rawb_clks
ffff800081186170 d cam_rawa_clks
ffff800081186230 d cam_main_clks
ffff800081186870 d cam_cg_regs
ffff800081186880 d of_match_clk_mt8188_ccu
ffff800081186a10 d ccu_desc
ffff800081186a98 d ccu_clks
ffff800081186b58 d ccu_cg_regs
ffff800081186b68 d of_match_clk_mt8188_imgsys_main
ffff8000811870e0 d imgsys1_dip_nr_desc
ffff800081187168 d imgsys1_dip_top_desc
ffff8000811871f0 d imgsys_wpe3_desc
ffff800081187278 d imgsys_wpe2_desc
ffff800081187300 d imgsys_wpe1_desc
ffff800081187388 d imgsys_main_desc
ffff800081187410 d img_sys_rst_desc
ffff800081187438 d imgsys1_dip_nr_clks
ffff8000811874b8 d imgsys1_dip_top_clks
ffff800081187538 d imgsys_wpe3_clks
ffff8000811875b8 d imgsys_wpe2_clks
ffff800081187638 d imgsys_wpe1_clks
ffff8000811876b8 d imgsys_main_clks
ffff800081187938 d imgsys_cg_regs
ffff800081187948 d of_match_clk_mt8188_imp_iic_wrap
ffff800081187c68 d imp_iic_wrap_en_desc
ffff800081187cf0 d imp_iic_wrap_w_desc
ffff800081187d78 d imp_iic_wrap_c_desc
ffff800081187e00 d imp_iic_wrap_en_clks
ffff800081187e80 d imp_iic_wrap_w_clks
ffff800081187f00 d imp_iic_wrap_c_clks
ffff800081187fc0 d imp_iic_wrap_cg_regs
ffff800081187fd0 d of_match_clk_mt8188_ipe
ffff800081188160 d ipe_desc
ffff8000811881e8 d ipe_sys_rst_desc
ffff800081188210 d ipe_clks
ffff800081188350 d ipe_cg_regs
ffff800081188360 d of_match_clk_mt8188_mfgcfg
ffff8000811884f0 d mfgcfg_desc
ffff800081188578 d mfgcfg_clks
ffff8000811885b8 d mfgcfg_cg_regs
ffff8000811885c8 d of_match_clk_mt8188_vdec
ffff800081188820 d vdec2_desc
ffff8000811888a8 d vdec1_desc
ffff800081188930 d vdec2_clks
ffff800081188a70 d vdec1_clks
ffff800081188c30 d vdec2_cg_regs
ffff800081188c40 d vdec1_cg_regs
ffff800081188c50 d vdec0_cg_regs
ffff800081188c60 d clk_mt8188_vdo0_id_table
ffff800081188ca0 d vdo0_desc
ffff800081188d28 d vdo0_clks
ffff800081189568 d vdo0_2_cg_regs
ffff800081189578 d vdo0_1_cg_regs
ffff800081189588 d vdo0_0_cg_regs
ffff800081189598 d clk_mt8188_vdo1_id_table
ffff8000811895d8 d vdo1_desc
ffff800081189660 d vdo1_clks
ffff80008118a5e0 d vdo1_5_cg_regs
ffff80008118a5f0 d vdo1_4_cg_regs
ffff80008118a600 d vdo1_3_cg_regs
ffff80008118a610 d vdo1_2_cg_regs
ffff80008118a620 d vdo1_1_cg_regs
ffff80008118a630 d vdo1_0_cg_regs
ffff80008118a640 d of_match_clk_mt8188_venc1
ffff80008118a7d0 d venc1_desc
ffff80008118a858 d venc1_clks
ffff80008118aa18 d venc1_cg_regs
ffff80008118aa28 d clk_mt8188_vpp0_id_table
ffff80008118aa68 d vpp0_desc
ffff80008118aaf0 d vpp0_clks
ffff80008118b630 d vpp0_2_cg_regs
ffff80008118b640 d vpp0_1_cg_regs
ffff80008118b650 d vpp0_0_cg_regs
ffff80008118b660 d clk_mt8188_vpp1_id_table
ffff80008118b6a0 d vpp1_desc
ffff80008118b728 d vpp1_clks
ffff80008118c428 d vpp1_1_cg_regs
ffff80008118c438 d vpp1_0_cg_regs
ffff80008118c448 d of_match_clk_mt8188_wpe
ffff80008118c6a0 d wpe_vpp0_desc
ffff80008118c728 d wpe_top_desc
ffff80008118c7b0 d wpe_vpp0_clks
ffff80008118cd70 d wpe_top_clks
ffff80008118ce70 d wpe_vpp0_1_cg_regs
ffff80008118ce80 d wpe_vpp0_0_cg_regs
ffff80008118ce90 d wpe_top_cg_regs
ffff80008118cea0 d apmixed_clks
ffff80008118cee0 d plls
ffff80008118d480 d of_match_clk_mt8192_apmixed
ffff80008118d610 d apmixed_cg_regs
ffff80008118d620 d of_match_clk_mt8192
ffff80008118d940 d topck_desc
ffff80008118d9c8 d peri_desc
ffff80008118da50 d infra_desc
ffff80008118dad8 d clk_rst_desc
ffff80008118db00 d top_clks
ffff80008118db80 d top_cg_regs
ffff80008118db90 d peri_clks
ffff80008118dbd0 d peri_cg_regs
ffff80008118dbe0 d infra_clks
ffff80008118fa20 d infra5_cg_regs
ffff80008118fa30 d infra4_cg_regs
ffff80008118fa40 d infra3_cg_regs
ffff80008118fa50 d infra2_cg_regs
ffff80008118fa60 d infra1_cg_regs
ffff80008118fa70 d infra0_cg_regs
ffff80008118fa80 d top_mtk_muxes
ffff8000811910a0 d apll_i2s_m_parents
ffff8000811910b0 d sflash_parents
ffff8000811910d0 d aes_msdcfde_parents
ffff800081191100 d spmi_mst_parents
ffff800081191138 d audio_h_parents
ffff800081191158 d pwm_parents
ffff800081191168 d camtm_parents
ffff800081191188 d vdec_parents
ffff800081191208 d venc_parents
ffff800081191288 d dpmaif_main_parents
ffff8000811912b0 d adsp_parents
ffff8000811912f0 d aud_2_parents
ffff800081191300 d aud_1_parents
ffff800081191310 d ufs_parents
ffff800081191348 d aes_ufsfde_parents
ffff800081191380 d aud_engen2_parents
ffff8000811913a0 d aud_engen1_parents
ffff8000811913c0 d dxcc_parents
ffff8000811913e0 d tl_parents
ffff8000811913f8 d seninf_parents
ffff800081191438 d i2c_parents
ffff800081191450 d ssusb_xhci_parents
ffff800081191470 d usb_top_parents
ffff800081191490 d disp_pwm_parents
ffff8000811914b8 d scam_parents
ffff8000811914c8 d dpi_parents
ffff8000811914f0 d atb_parents
ffff800081191508 d pwrap_ulposc_parents
ffff800081191530 d aud_intbus_parents
ffff800081191548 d audio_parents
ffff800081191568 d msdc30_parents
ffff800081191590 d msdc50_0_parents
ffff8000811915c0 d msdc50_0_h_parents
ffff8000811915d8 d spi_parents
ffff8000811915f8 d uart_parents
ffff800081191608 d camtg_parents
ffff800081191648 d mfg_pll_parents
ffff800081191658 d mfg_ref_parents
ffff800081191678 d dsp7_parents
ffff8000811916b8 d ccu_parents
ffff800081191708 d cam_parents
ffff800081191758 d dpe_parents
ffff800081191798 d ipe_parents
ffff8000811917e0 d img_parents
ffff800081191840 d mdp_parents
ffff800081191898 d disp_parents
ffff8000811918e8 d bus_aximem_parents
ffff800081191910 d scp_parents
ffff800081191950 d spm_parents
ffff800081191970 d axi_parents
ffff8000811919a8 d top_divs
ffff8000811924e8 d top_fixed_clks
ffff800081192508 d of_match_clk_mt8192_aud
ffff800081192698 d aud_desc
ffff800081192720 d aud_clks
ffff800081192f20 d aud2_cg_regs
ffff800081192f30 d aud1_cg_regs
ffff800081192f40 d aud0_cg_regs
ffff800081192f50 d of_match_clk_mt8192_cam
ffff800081193338 d cam_rawc_desc
ffff8000811933c0 d cam_rawb_desc
ffff800081193448 d cam_rawa_desc
ffff8000811934d0 d cam_desc
ffff800081193558 d cam_rawc_clks
ffff800081193618 d cam_rawb_clks
ffff8000811936d8 d cam_rawa_clks
ffff800081193798 d cam_clks
ffff800081193b98 d cam_cg_regs
ffff800081193ba8 d of_match_clk_mt8192_img
ffff800081193e00 d img2_desc
ffff800081193e88 d img_desc
ffff800081193f10 d img2_clks
ffff800081194090 d img_clks
ffff800081194190 d img_cg_regs
ffff8000811941a0 d of_match_clk_mt8192_imp_iic_wrap
ffff800081194718 d imp_iic_wrap_ws_desc
ffff8000811947a0 d imp_iic_wrap_w_desc
ffff800081194828 d imp_iic_wrap_s_desc
ffff8000811948b0 d imp_iic_wrap_n_desc
ffff800081194938 d imp_iic_wrap_e_desc
ffff8000811949c0 d imp_iic_wrap_c_desc
ffff800081194a48 d imp_iic_wrap_ws_clks
ffff800081194b08 d imp_iic_wrap_w_clks
ffff800081194b48 d imp_iic_wrap_s_clks
ffff800081194c08 d imp_iic_wrap_n_clks
ffff800081194c88 d imp_iic_wrap_e_clks
ffff800081194cc8 d imp_iic_wrap_c_clks
ffff800081194dc8 d imp_iic_wrap_cg_regs
ffff800081194dd8 d of_match_clk_mt8192_ipe
ffff800081194f68 d ipe_desc
ffff800081194ff0 d ipe_clks
ffff8000811951f0 d ipe_cg_regs
ffff800081195200 d of_match_clk_mt8192_mdp
ffff800081195390 d mdp_desc
ffff800081195418 d mdp_clks
ffff800081195998 d mdp1_cg_regs
ffff8000811959a8 d mdp0_cg_regs
ffff8000811959b8 d of_match_clk_mt8192_mfg
ffff800081195b48 d mfg_desc
ffff800081195bd0 d mfg_clks
ffff800081195c10 d mfg_cg_regs
ffff800081195c20 d clk_mt8192_mm_id_table
ffff800081195c60 d mm_desc
ffff800081195ce8 d mm_clks
ffff8000811965e8 d mm2_cg_regs
ffff8000811965f8 d mm1_cg_regs
ffff800081196608 d mm0_cg_regs
ffff800081196618 d of_match_clk_mt8192_msdc
ffff8000811967a8 d msdc_top_desc
ffff800081196830 d msdc_top_clks
ffff800081196bf0 d msdc_top_cg_regs
ffff800081196c00 d of_match_clk_mt8192_scp_adsp
ffff800081196d90 d scp_adsp_desc
ffff800081196e18 d scp_adsp_clks
ffff800081196e58 d scp_adsp_cg_regs
ffff800081196e68 d of_match_clk_mt8192_vdec
ffff8000811970c0 d vdec_soc_desc
ffff800081197148 d vdec_desc
ffff8000811971d0 d vdec_soc_clks
ffff800081197310 d vdec_clks
ffff800081197450 d vdec2_cg_regs
ffff800081197460 d vdec1_cg_regs
ffff800081197470 d vdec0_cg_regs
ffff800081197480 d of_match_clk_mt8192_venc
ffff800081197610 d venc_desc
ffff800081197698 d venc_clks
ffff800081197798 d venc_cg_regs
ffff8000811977a8 d apmixed_clks
ffff8000811977e8 d plls
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ffff80008119d880 d spm_parents
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ffff8000811a0340 d cam_rawb_desc
ffff8000811a03c8 d cam_rawa_desc
ffff8000811a0450 d cam_mraw_desc
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ffff8000811a07a0 d cam_rawa_clks
ffff8000811a0860 d cam_mraw_clks
ffff8000811a09e0 d cam_clks
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ffff8000811a16c0 d img1_wpe_desc
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ffff8000811a17d0 d img1_dip_top_desc
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ffff8000811a1960 d img1_dip_nr_clks
ffff8000811a19e0 d img1_dip_top_clks
ffff8000811a1a60 d img_clks
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ffff8000811a1d30 d of_match_clk_mt8195_imp_iic_wrap
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ffff8000811a2010 d imp_iic_wrap_s_desc
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ffff8000811a21d8 d imp_iic_wrap_s_clks
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ffff8000811a22a8 d of_match_clk_mt8195_ipe
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ffff8000811a3e20 d vdo0_1_cg_regs
ffff8000811a3e30 d vdo0_0_cg_regs
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ffff8000811a4bd8 d vdo1_3_cg_regs
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ffff8000811a5de8 d vpp0_1_cg_regs
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ffff8000811aa920 d mcupm_parents
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ffff8000811aaa90 d usb_1p_parents
ffff8000811aaaa0 d disp_pwm_parents
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ffff8000811ac190 d dvo_parents
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ffff8000811ac308 d mdp_parents
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ffff8000811ac3b8 d dp0_parents
ffff8000811ac3e0 d dp1_parents
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ffff8000811ac580 d dpe_parents
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ffff8000811ac6d0 d img1_parents
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ffff8000811ae400 d vlp_aud_engen1_parents
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ffff8000811ae4f8 d vlp_camtg2_7_parents
ffff8000811ae558 d vlp_camtg0_1_parents
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ffff8000811ae608 d vlp_axi_vlp_parents
ffff8000811ae630 d vlp_pwm_vlp_parents
ffff8000811ae658 d vlp_dvfsrc_parents
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ffff8000811b3218 d of_match_clk_mt8365
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ffff8000811b4a40 d ifr5_cg_regs
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ffff8000811b4a60 d ifr3_cg_regs
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ffff8000811b61c8 d gcpu_cpm_parents
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ffff8000811b6208 d eth_parents
ffff8000811b6230 d ecc_parents
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ffff8000811b6398 d i2c_parents
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ffff8000811b6480 d aud_1_parents
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ffff8000811b64c8 d msdc30_1_parents
ffff8000811b6508 d msdc50_2_parents
ffff8000811b6548 d msdc50_0_parents
ffff8000811b6588 d msdc50_0_hc_parents
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ffff8000811b65d8 d camtg_parents
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ffff8000811b7060 d of_match_clk_mt8365_apu
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ffff8000811b7408 d of_match_clk_mt8365_cam
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ffff8000811b7820 d cam_cg_regs
ffff8000811b7830 d of_match_clk_mt8365_mfg
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ffff8000811b7ac8 d mfg1_cg_regs
ffff8000811b7ad8 d mfg0_cg_regs
ffff8000811b7ae8 d clk_mt8365_mm_id_table
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ffff8000811b84b0 d mm1_cg_regs
ffff8000811b84c0 d mm0_cg_regs
ffff8000811b84d0 d of_match_clk_mt8365_vdec
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ffff8000811b8768 d vdec1_cg_regs
ffff8000811b8778 d vdec0_cg_regs
ffff8000811b8788 d of_match_clk_mt8365_venc
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ffff8000811b8a20 d venc_cg_regs
ffff8000811b8a30 d plls
ffff8000811b8d90 d of_match_clk_mt8516_apmixed
ffff8000811b8f20 d mmpll_div_table
ffff8000811b8f80 d of_match_clk_mt8516
ffff8000811b91d8 d infra_desc
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ffff8000811b92e8 d top_clks
ffff8000811ba868 d top5_cg_regs
ffff8000811ba878 d top4_cg_regs
ffff8000811ba888 d top3_cg_regs
ffff8000811ba898 d top2_cg_regs
ffff8000811ba8a8 d top1_cg_regs
ffff8000811ba8b8 d top_adj_divs
ffff8000811baa68 d __func__.0
ffff8000811baa80 d meson_aoclk_reset_ops
ffff8000811baaa0 D meson_clk_cpu_dyndiv_ops
ffff8000811bab68 D meson_clk_dualdiv_ro_ops
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ffff800081e97b20 d iort_arm_smmu_v3_cfg
ffff800081e97b58 d __setup_str_pnp_setup_reserve_mem
ffff800081e97b69 d __setup_str_pnp_setup_reserve_io
ffff800081e97b79 d __setup_str_pnp_setup_reserve_dma
ffff800081e97b8a d __setup_str_pnp_setup_reserve_irq
ffff800081e97b9b d __setup_str_pnpacpi_setup
ffff800081e97ba4 d __setup_str_clk_ignore_unused_setup
ffff800081e97bb8 d quirk_index
ffff800081e97bc0 d wdt_mux_p
ffff800081e97bd0 d usb_frmcnt_parents
ffff800081e97be0 d u2u3_sys_parents
ffff800081e97bf0 d u2u3_parents
ffff800081e97c00 d a_tuner_parents
ffff800081e97c18 d aud_l_parents
ffff800081e97c30 d a1sys_parents
ffff800081e97c40 d aud_parents
ffff800081e97c50 d eip97b_parents
ffff800081e97c78 d sgm_reg_parents
ffff800081e97c88 d sgm_325m_parents
ffff800081e97c98 d netsys_2x_parents
ffff800081e97cb0 d netsys_mcu_parents
ffff800081e97cd8 d netsys_500m_parents
ffff800081e97ce8 d netsys_parents
ffff800081e97cf8 d ap2cnn_host_parents
ffff800081e97d08 d arm_db_main_parents
ffff800081e97d18 d sysapb_parents
ffff800081e97d28 d sysaxi_parents
ffff800081e97d38 d dramc_md32_parents
ffff800081e97d50 d csw_f26m_parents
ffff800081e97d60 d emmc_400m_parents
ffff800081e97d80 d emmc_208m_parents
ffff800081e97db8 d pextp_tl_ck_parents
ffff800081e97dd8 d i2c_parents
ffff800081e97df8 d pwm_parents
ffff800081e97e28 d uart_parents
ffff800081e97e40 d spi_parents
ffff800081e97e80 d spinfi_parents
ffff800081e97ec0 d nfi1x_parents
ffff800081e97f00 d infra_pcie_parents
ffff800081e97f20 d infra_pwm_bsel_parents
ffff800081e97f40 d infra_pwm1_parents
ffff800081e97f48 d infra_spi1_parents
ffff800081e97f58 d infra_spi0_parents
ffff800081e97f68 d infra_uart_parent
ffff800081e97f78 d da_u2_refsel_parents
ffff800081e97f88 d u2u3_sys_parents
ffff800081e97f98 d a_tuner_parents
ffff800081e97fb0 d aud_l_parents
ffff800081e97fc8 d eip_b_parents
ffff800081e97fd8 d conn_mcusys_parents
ffff800081e97fe8 d a1sys_parents
ffff800081e97ff8 d sgm_reg_parents
ffff800081e98008 d sgm_325m_parents
ffff800081e98018 d netsys_2x_parents
ffff800081e98038 d netsys_mcu_parents
ffff800081e98060 d netsys_500m_parents
ffff800081e98070 d netsys_parents
ffff800081e98080 d arm_db_jtsel_parents
ffff800081e98090 d arm_db_main_parents
ffff800081e980a0 d sysapb_parents
ffff800081e980b8 d sysaxi_parents
ffff800081e980d0 d dramc_md32_parents
ffff800081e980e0 d f_26m_adc_parents
ffff800081e980f0 d emmc_416m_parents
ffff800081e98100 d emmc_250m_parents
ffff800081e98110 d pextp_tl_ck_parents
ffff800081e98130 d i2c_parents
ffff800081e98150 d pwm_parents
ffff800081e98170 d uart_parents
ffff800081e98188 d spi_parents
ffff800081e981c8 d spinfi_parents
ffff800081e98208 d nfi1x_parents
ffff800081e98248 d infra_pcie_parents
ffff800081e98268 d infra_pwm_bsel_parents
ffff800081e98288 d infra_spi_parents
ffff800081e98298 d infra_uart_parent
ffff800081e982a8 d infra_pcie_gfmux_tl_ck_o_p3_parents
ffff800081e982c8 d infra_pcie_gfmux_tl_ck_o_p2_parents
ffff800081e982e8 d infra_pcie_gfmux_tl_ck_o_p1_parents
ffff800081e98308 d infra_pcie_gfmux_tl_ck_o_p0_parents
ffff800081e98328 d infra_pwm_bck_parents
ffff800081e98348 d infra_mux_spi1_parents
ffff800081e98358 d infra_mux_spi0_parents
ffff800081e98368 d infra_mux_uart2_parents
ffff800081e98378 d infra_mux_uart1_parents
ffff800081e98388 d infra_mux_uart0_parents
ffff800081e98398 d ifr_muxes
ffff800081e984b0 d ifr_i2c0_parents
ffff800081e984c0 d ifr_eth_25m_parents
ffff800081e984d0 d ifr_mux1_parents
ffff800081e984f0 d nfiecc_parents
ffff800081e98518 d csw_nfiecc_parents
ffff800081e98540 d dbg_atclk_parents
ffff800081e98568 d bsi_parents
ffff800081e98588 d uart2_parents
ffff800081e98598 d aud_spdifin_parents
ffff800081e985a8 d spi_parents
ffff800081e985c8 d pwm_parents
ffff800081e985d8 d aud_i2s0_m_parents
ffff800081e985e8 d i2c_parents
ffff800081e98608 d aud_engen2_parents
ffff800081e98628 d aud_engen1_parents
ffff800081e98648 d aud2_parents
ffff800081e98658 d aud1_parents
ffff800081e98668 d eth_parents
ffff800081e98690 d msdc2_parents
ffff800081e986d0 d spinor_parents
ffff800081e98710 d usb_78m_parents
ffff800081e98738 d nfi1x_pad_parents
ffff800081e98748 d nfi2x_pad_parents
ffff800081e989f0 d aud_intbus_parents
ffff800081e98a18 d qaxi_aud26m_parents
ffff800081e98a28 d pmicspi_parents
ffff800081e98a48 d msdc1_parents
ffff800081e98a88 d uart1_parents
ffff800081e98a98 d msdc0_parents
ffff800081e98ad8 d ahb_infra_parents
ffff800081e98b40 d uart0_parents
ffff800081e98b50 d top_divs
ffff800081e99208 d fixed_clks
ffff800081e99268 d mux_armclk_p
ffff800081e99278 d px30_cru_critical_clocks
ffff800081e99310 d mux_gpu_p
ffff800081e99320 d mux_mipidsiphy_ref_p
ffff800081e99330 d mux_usbphy_ref_p
ffff800081e99340 d mux_uart0_pmu_p
ffff800081e99358 d mux_wifi_pmu_p
ffff800081e99368 d mux_rtc32k_pmu_p
ffff800081e99380 d mux_gmac_rmii_sel_p
ffff800081e99390 d mux_gmac_p
ffff800081e993a0 d mux_sdmmc_p
ffff800081e993b0 d mux_emmc_p
ffff800081e993c0 d mux_sdio_p
ffff800081e993d0 d mux_nandc_p
ffff800081e993e0 d mux_dclk_vopl_p
ffff800081e993f8 d mux_dclk_vopb_p
ffff800081e99410 d mux_cif_out_p
ffff800081e99430 d mux_uart5_p
ffff800081e99448 d mux_uart4_p
ffff800081e99460 d mux_uart3_p
ffff800081e99478 d mux_uart2_p
ffff800081e99490 d mux_uart1_p
ffff800081e994a8 d mux_uart_src_p
ffff800081e994c8 d mux_i2s0_rx_tx_p
ffff800081e994d8 d mux_i2s0_tx_rx_p
ffff800081e994e8 d mux_i2s2_out_p
ffff800081e994f8 d mux_i2s1_out_p
ffff800081e99508 d mux_i2s0_rx_out_p
ffff800081e99520 d mux_i2s0_tx_out_p
ffff800081e99538 d mux_i2s2_p
ffff800081e99558 d mux_i2s1_p
ffff800081e99578 d mux_i2s0_rx_p
ffff800081e99598 d mux_i2s0_tx_p
ffff800081e995b8 d mux_pdm_p
ffff800081e995c8 d mux_gpll_xin24m_npll_p
ffff800081e995e0 d mux_gpll_cpll_npll_xin24m_p
ffff800081e99600 d mux_gpll_cpll_npll_p
ffff800081e99618 d mux_gpll_xin24m_p
ffff800081e99628 d mux_gpll_npll_p
ffff800081e99638 d mux_gpll_cpll_p
ffff800081e99648 d mux_npll_cpll_p
ffff800081e99658 d mux_cpll_npll_p
ffff800081e99668 d mux_4plls_p
ffff800081e99688 d mux_ddrstdby_p
ffff800081e99698 d mux_ddrphy_p
ffff800081e996a8 d mux_usb480m_p
ffff800081e996c0 d mux_pll_p
ffff800081e996c8 d rk3308_critical_clocks
ffff800081e99718 d mux_armclk_p
ffff800081e99730 d mux_spdif_rx_p
ffff800081e99740 d mux_spdif_rx_src_p
ffff800081e99750 d mux_spdif_tx_p
ffff800081e99768 d mux_spdif_tx_src_p
ffff800081e99778 d mux_i2s1_2ch_out_p
ffff800081e99788 d mux_i2s1_2ch_p
ffff800081e997a0 d mux_i2s0_2ch_out_p
ffff800081e997b0 d mux_i2s0_2ch_p
ffff800081e997c8 d mux_i2s3_8ch_rx_tx_p
ffff800081e997d8 d mux_i2s3_8ch_rx_p
ffff800081e997f0 d mux_i2s3_8ch_tx_out_p
ffff800081e99800 d mux_i2s3_8ch_tx_rx_p
ffff800081e99810 d mux_i2s3_8ch_tx_p
ffff800081e99828 d mux_i2s2_8ch_rx_tx_p
ffff800081e99838 d mux_i2s2_8ch_rx_p
ffff800081e99850 d mux_i2s2_8ch_tx_out_p
ffff800081e99860 d mux_i2s2_8ch_tx_rx_p
ffff800081e99870 d mux_i2s2_8ch_tx_p
ffff800081e99888 d mux_i2s1_8ch_rx_tx_p
ffff800081e99898 d mux_i2s1_8ch_rx_p
ffff800081e998b0 d mux_i2s1_8ch_tx_out_p
ffff800081e998c0 d mux_i2s1_8ch_tx_rx_p
ffff800081e998d0 d mux_i2s1_8ch_tx_p
ffff800081e998e8 d mux_i2s0_8ch_rx_tx_p
ffff800081e998f8 d mux_i2s0_8ch_rx_p
ffff800081e99910 d mux_i2s0_8ch_tx_out_p
ffff800081e99920 d mux_i2s0_8ch_tx_rx_p
ffff800081e99930 d mux_i2s0_8ch_tx_p
ffff800081e99948 d mux_pdm_p
ffff800081e99958 d mux_wifi_p
ffff800081e99968 d mux_wifi_src_p
ffff800081e99978 d mux_usbphy_ref_p
ffff800081e99988 d mux_rtc32k_p
ffff800081e999a8 d mux_ddrstdby_p
ffff800081e999b8 d mux_mac_rmii_sel_p
ffff800081e999c8 d mux_mac_p
ffff800081e999d8 d mux_emmc_p
ffff800081e999e8 d mux_sdio_p
ffff800081e999f8 d mux_sdmmc_p
ffff800081e99a08 d mux_nandc_p
ffff800081e99a18 d mux_dclk_vop_p
ffff800081e99a30 d mux_uart4_p
ffff800081e99a48 d mux_uart3_p
ffff800081e99a60 d mux_uart2_p
ffff800081e99a78 d mux_uart1_p
ffff800081e99a90 d mux_uart0_p
ffff800081e99aa8 d mux_vpll0_vpll1_xin24m_p
ffff800081e99ac0 d mux_vpll0_vpll1_p
ffff800081e99ad0 d mux_dpll_vpll0_vpll1_usb480m_xin24m_p
ffff800081e99af8 d mux_dpll_vpll0_vpll1_xin24m_p
ffff800081e99b18 d mux_dpll_vpll0_vpll1_p
ffff800081e99b30 d mux_dpll_vpll0_xin24m_p
ffff800081e99b48 d mux_dpll_vpll0_p
ffff800081e99b58 d mux_usb480m_p
ffff800081e99b70 d mux_pll_p
ffff800081e99b78 d rk3328_critical_clocks
ffff800081e99cf8 d mux_armclk_p
ffff800081e99d18 d mux_mac2io_ext_p
ffff800081e99d28 d mux_mac2phy_src_p
ffff800081e99d38 d mux_mac2io_src_p
ffff800081e99d48 d mux_xin24m_32k_p
ffff800081e99d58 d mux_ref_usb3otg_src_p
ffff800081e99d68 d mux_aclk_peri_pre_p
ffff800081e99d80 d mux_dclk_lcdc_p
ffff800081e99d90 d mux_sclk_cif_p
ffff800081e99da0 d mux_uart2_p
ffff800081e99db8 d mux_uart1_p
ffff800081e99dd0 d mux_uart0_p
ffff800081e99de8 d mux_spdif_p
ffff800081e99e08 d mux_i2s2out_p
ffff800081e99e18 d mux_i2s1out_p
ffff800081e99e28 d mux_i2s2_p
ffff800081e99e48 d mux_i2s1_p
ffff800081e99e68 d mux_i2s0_p
ffff800081e99e88 d mux_usb480m_p
ffff800081e99e98 d mux_hdmiphy_p
ffff800081e99ea8 d mux_ddrphy_p
ffff800081e99ec0 d mux_2plls_24m_u480m_p
ffff800081e99ee0 d mux_2plls_u480m_p
ffff800081e99ef8 d mux_4plls_p
ffff800081e99f18 d mux_2plls_hdmiphy_p
ffff800081e99f30 d mux_2plls_xin24m_p
ffff800081e99f48 d mux_cpll_gpll_apll_p
ffff800081e99f60 d mux_gpll_cpll_p
ffff800081e99f70 d mux_2plls_p
ffff800081e99f80 d mux_pll_p
ffff800081e99f88 d rk3368_critical_clocks
ffff800081e99fd8 d mux_armclkb_p
ffff800081e99fe8 d mux_armclkl_p
ffff800081e99ff8 d mux_mmc_src_p
ffff800081e9a018 d mux_mac_p
ffff800081e9a028 d mux_uart4_p
ffff800081e9a040 d mux_uart3_p
ffff800081e9a058 d mux_uart2_p
ffff800081e9a068 d mux_uart1_p
ffff800081e9a080 d mux_uart0_p
ffff800081e9a098 d mux_hsicphy480m_p
ffff800081e9a0b0 d mux_hsic_usbphy480m_p
ffff800081e9a0c0 d mux_usbphy480m_p
ffff800081e9a0d0 d mux_vip_out_p
ffff800081e9a0e0 d mux_edp_24m_p
ffff800081e9a0f0 d mux_spdif_8ch_p
ffff800081e9a110 d mux_i2s_2ch_p
ffff800081e9a130 d mux_i2s_8ch_clkout_p
ffff800081e9a140 d mux_i2s_8ch_pre_p
ffff800081e9a160 d mux_pll_src_cpll_gpll_npll_usb_p
ffff800081e9a180 d mux_pll_src_cpll_gpll_npll_npll_p
ffff800081e9a1a0 d mux_pll_src_cpll_gpll_usb_npll_p
ffff800081e9a1c0 d mux_pll_src_cpll_gpll_usb_usb_p
ffff800081e9a1e0 d mux_pll_src_cpll_gpll_usb_p
ffff800081e9a1f8 d mux_pll_src_npll_cpll_gpll_p
ffff800081e9a210 d mux_pll_src_cpll_gpll_npll_p
ffff800081e9a228 d mux_pll_src_cpll_gpll_p
ffff800081e9a238 d mux_aclk_bus_src_p
ffff800081e9a248 d mux_cs_src_p
ffff800081e9a260 d mux_ddrphy_p
ffff800081e9a270 d mux_pll_p
ffff800081e9a280 d mux_armclkl_p
ffff800081e9a2a0 d mux_armclkb_p
ffff800081e9a2c0 d rk3399_cru_critical_clocks
ffff800081e9a3b0 d rk3399_pmucru_critical_clocks
ffff800081e9a3d8 d mux_clk_testout2_2io_p
ffff800081e9a3e8 d mux_uart4_pmu_p
ffff800081e9a400 d mux_wifi_pmu_p
ffff800081e9a410 d mux_fclk_cm0s_pmu_ppll_p
ffff800081e9a420 d mux_24m_ppll_p
ffff800081e9a430 d mux_ppll_24m_p
ffff800081e9a440 d mux_uart3_p
ffff800081e9a458 d mux_uart2_p
ffff800081e9a470 d mux_uart1_p
ffff800081e9a488 d mux_uart0_p
ffff800081e9a4a0 d mux_i2sout_p
ffff800081e9a4b0 d mux_i2sch_p
ffff800081e9a4c8 d mux_i2s2_p
ffff800081e9a4e8 d mux_i2s1_p
ffff800081e9a508 d mux_i2s0_p
ffff800081e9a528 d mux_spdif_p
ffff800081e9a548 d mux_rmii_p
ffff800081e9a558 d mux_aclk_gmac_p
ffff800081e9a568 d mux_usbphy_480m_p
ffff800081e9a578 d mux_clk_testout2_p
ffff800081e9a588 d mux_clk_testout1_p
ffff800081e9a598 d mux_hclk_perilp1_p
ffff800081e9a5a8 d mux_fclk_cm0s_p
ffff800081e9a5b8 d mux_aclk_perilp0_p
ffff800081e9a5c8 d mux_aclk_emmc_p
ffff800081e9a5d8 d mux_pciecore_cru_phy_p
ffff800081e9a5e8 d mux_pll_src_24m_32k_cpll_gpll_p
ffff800081e9a608 d mux_pll_src_24m_pciephy_p
ffff800081e9a618 d mux_pll_src_24m_usbphy480m_p
ffff800081e9a628 d mux_clk_cif_p
ffff800081e9a638 d mux_dclk_vop1_p
ffff800081e9a648 d mux_dclk_vop0_p
ffff800081e9a658 d mux_pll_src_vpll_cpll_gpll_24m_p
ffff800081e9a678 d mux_pll_src_vpll_cpll_gpll_npll_p
ffff800081e9a698 d mux_pll_src_vpll_cpll_gpll_p
ffff800081e9a6b0 d mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p
ffff800081e9a6e0 d mux_pll_src_cpll_gpll_npll_upll_24m_p
ffff800081e9a708 d mux_pll_src_ppll_cpll_gpll_npll_p
ffff800081e9a730 d mux_pll_src_cpll_gpll_npll_usbphy480m_p
ffff800081e9a750 d mux_pll_src_cpll_gpll_npll_24m_p
ffff800081e9a770 d mux_pll_src_cpll_gpll_npll_ppll_p
ffff800081e9a790 d mux_pll_src_npll_cpll_gpll_p
ffff800081e9a7a8 d mux_pll_src_cpll_gpll_upll_p
ffff800081e9a7c0 d mux_pll_src_cpll_gpll_ppll_p
ffff800081e9a7d8 d mux_pll_src_cpll_gpll_npll_p
ffff800081e9a7f0 d mux_pll_src_cpll_gpll_p
ffff800081e9a800 d mux_aclk_perihp_p
ffff800081e9a810 d mux_cs_p
ffff800081e9a828 d mux_cci_trace_p
ffff800081e9a838 d mux_aclk_cci_p
ffff800081e9a858 d mux_ddrclk_p
ffff800081e9a878 d mux_pll_p
ffff800081e9a888 d mux_armclk
ffff800081e9a898 d clk_32k_p
ffff800081e9a8a8 d sclk_uart7_src_p
ffff800081e9a8c0 d sclk_uart6_src_p
ffff800081e9a8d8 d sclk_uart5_src_p
ffff800081e9a8f0 d sclk_uart4_src_p
ffff800081e9a908 d sclk_uart3_src_p
ffff800081e9a920 d sclk_uart2_src_p
ffff800081e9a938 d sclk_uart1_src_p
ffff800081e9a950 d sclk_uart0_src_p
ffff800081e9a968 d mclk_spdif_src_p
ffff800081e9a980 d mclk_sai_i2s1_p
ffff800081e9a990 d mclk_sai_i2s0_p
ffff800081e9a9a0 d mclk_i2s3_8ch_sai_src_p
ffff800081e9a9b8 d mclk_i2s2_2ch_sai_src_p
ffff800081e9a9d0 d mclk_i2s1_8ch_sai_src_p
ffff800081e9a9e8 d mclk_i2s0_2ch_sai_src_p
ffff800081e9aa00 d dclk_vop0_p
ffff800081e9aa10 d clk_ref_pcie_inner_phy_p
ffff800081e9aa20 d clk_i2c2_p
ffff800081e9aa40 d aclk_rkvdec_pvtmux_root_p
ffff800081e9aa50 d aclk_gpu_p
ffff800081e9aa60 d mux_600m_300m_200m_24m_p
ffff800081e9aa80 d mux_500m_300m_100m_24m_p
ffff800081e9aaa0 d mux_500m_200m_100m_24m_p
ffff800081e9aac0 d mux_339m_200m_100m_24m_p
ffff800081e9aae0 d mux_300m_200m_100m_24m_p
ffff800081e9ab00 d mux_200m_100m_50m_24m_p
ffff800081e9ab20 d mux_200m_100m_24m_p
ffff800081e9ab38 d mux_150m_100m_24m_p
ffff800081e9ab50 d mux_100m_50m_24m_p
ffff800081e9ab68 d mux_gpll_cpll_xin24m_p
ffff800081e9ab80 d mux_gpll_cpll_p
ffff800081e9ab90 d mux_24m_32k_p
ffff800081e9aba0 d mux_pll_p
ffff800081e9aba8 d clk_mipidsi_ref_p
ffff800081e9abb8 d clk_usbphy_ref_p
ffff800081e9abc8 d clk_pipephy_ref_p
ffff800081e9abd8 d clk_pmu1_uart0_p
ffff800081e9abf0 d clk_rtc32k_pmu_p
ffff800081e9ac08 d clk_uart9_p
ffff800081e9ac20 d clk_uart8_p
ffff800081e9ac38 d clk_uart7_p
ffff800081e9ac50 d clk_uart6_p
ffff800081e9ac68 d clk_uart5_p
ffff800081e9ac80 d clk_uart4_p
ffff800081e9ac98 d clk_uart3_p
ffff800081e9acb0 d clk_uart2_p
ffff800081e9acc8 d clk_uart1_p
ffff800081e9ace0 d clk_spdif_p
ffff800081e9acf8 d mclk_sai2_out2io_p
ffff800081e9ad08 d clk_sai2_p
ffff800081e9ad28 d mclk_sai1_out2io_p
ffff800081e9ad38 d clk_sai1_p
ffff800081e9ad58 d mclk_sai0_out2io_p
ffff800081e9ad68 d clk_sai0_p
ffff800081e9ad88 d mux_200m_100m_50m_xin24m_p
ffff800081e9ada8 d mux_200m_100m_p
ffff800081e9adb8 d mux_200m_xin24m_32k_p
ffff800081e9add0 d mux_125m_xin24m_p
ffff800081e9ade0 d mux_100m_50m_xin24m_p
ffff800081e9adf8 d mux_50m_xin24m_p
ffff800081e9ae08 d mux_xin24m_32k_p
ffff800081e9ae18 d vpll_dmyhpll_gpll_cpll_p
ffff800081e9ae38 d gpll_cpll_xin24m_dmyhpll_p
ffff800081e9ae58 d gpll_cpll_xin24m_dmyapll_p
ffff800081e9ae78 d gpll_cpll_xin24m_p
ffff800081e9ae90 d gpll_dmyhpll_vpll_apll_p
ffff800081e9aeb0 d gpll_cpll_vpll_dmyhpll_p
ffff800081e9aed0 d gpll_cpll_hpll_xin24m_p
ffff800081e9aef0 d gpll_cpll_pvtpll_dmyapll_p
ffff800081e9af10 d gpll_cpll_hpll_p
ffff800081e9af28 d gpll_cpll_p
ffff800081e9af38 d mux_pll_p
ffff800081e9af40 d rk3568_pmucru_critical_clocks
ffff800081e9af58 d mux_armclk_p
ffff800081e9af68 d rk3568_cru_critical_clocks
ffff800081e9b010 d clk_rkvdec_core_p
ffff800081e9b030 d aclk_rkvdec_pre_p
ffff800081e9b040 d clk_pwm0_p
ffff800081e9b050 d clk_mac_2top_p
ffff800081e9b070 d clk_pdpmu_p
ffff800081e9b080 d clk_hdmi_ref_p
ffff800081e9b090 d mux_gmac1_rx_tx_p
ffff800081e9b0a8 d mux_gmac1_rmii_speed_p
ffff800081e9b0b8 d mux_gmac1_rgmii_speed_p
ffff800081e9b0d8 d mux_gmac1_p
ffff800081e9b0e8 d mux_gmac0_rx_tx_p
ffff800081e9b100 d mux_gmac0_rmii_speed_p
ffff800081e9b110 d mux_gmac0_rgmii_speed_p
ffff800081e9b130 d mux_gmac0_p
ffff800081e9b140 d clk_pciephy2_ref_p
ffff800081e9b150 d clk_pciephy1_ref_p
ffff800081e9b160 d clk_pciephy0_ref_p
ffff800081e9b170 d clk_wifi_p
ffff800081e9b180 d clk_mipidsiphy1_ref_p
ffff800081e9b190 d clk_mipidsiphy0_ref_p
ffff800081e9b1a0 d clk_usbphy1_ref_p
ffff800081e9b1b0 d clk_usbphy0_ref_p
ffff800081e9b1c0 d ppll_usb480m_cpll_gpll_p
ffff800081e9b1e0 d xin24m_cpll100_p
ffff800081e9b1f0 d gpll400_gpll300_gpll200_xin24m_p
ffff800081e9b210 d cpll500_gpll400_gpll300_xin24m_p
ffff800081e9b230 d xin24m_32k_p
ffff800081e9b240 d gpll200_xin24m_cpll100_p
ffff800081e9b258 d gpll100_xin24m_cpll100_p
ffff800081e9b270 d gpll_cpll_usb480m_p
ffff800081e9b288 d xin24m_gpll100_cpll100_p
ffff800081e9b2a0 d gpll100_gpll75_cpll50_xin24m_p
ffff800081e9b2c0 d gpll400_cpll333_gpll200_p
ffff800081e9b2d8 d hpll_vpll_gpll_cpll_p
ffff800081e9b2f8 d cpll_gpll_hpll_vpll_p
ffff800081e9b318 d gpll300_cpll250_gpll100_xin24m_p
ffff800081e9b338 d gpll_usb480m_xin24m_p
ffff800081e9b358 d cpll_gpll_hpll_p
ffff800081e9b370 d cpll333_gpll300_gpll200_p
ffff800081e9b388 d clk_gmac_ptp_p
ffff800081e9b3a8 d cpll125_cpll50_cpll25_xin24m_p
ffff800081e9b3c8 d clk_sdmmc_p
ffff800081e9b3f8 d gpll300_gpll200_gpll100_xin24m_p
ffff800081e9b418 d gpll200_cpll125_p
ffff800081e9b428 d aclk_pipe_p
ffff800081e9b448 d cclk_emmc_p
ffff800081e9b478 d gpll200_gpll150_cpll125_p
ffff800081e9b490 d sclk_sfc_p
ffff800081e9b4c0 d clk_nandc_p
ffff800081e9b4e0 d gpll300_gpll200_gpll100_p
ffff800081e9b4f8 d gpll200_gpll150_gpll100_p
ffff800081e9b510 d clk_i2c_p
ffff800081e9b530 d mclk_pdm_p
ffff800081e9b550 d i2s3_mclkout_rx_p
ffff800081e9b560 d i2s3_mclkout_tx_p
ffff800081e9b570 d i2s2_mclkout_p
ffff800081e9b580 d i2s1_mclkout_rx_p
ffff800081e9b590 d i2s1_mclkout_tx_p
ffff800081e9b5a0 d i2s0_mclkout_rx_p
ffff800081e9b5b0 d i2s0_mclkout_tx_p
ffff800081e9b5c0 d gpll100_gpll75_gpll50_p
ffff800081e9b5d8 d gpll200_gpll150_gpll100_xin24m_p
ffff800081e9b5f8 d clk_ddr1x_p
ffff800081e9b608 d dpll_gpll_cpll_p
ffff800081e9b620 d clk_npu_p
ffff800081e9b630 d clk_npu_pre_ndft_p
ffff800081e9b640 d clk_gpu_pre_mux_p
ffff800081e9b650 d gpll150_gpll100_gpll75_xin24m_p
ffff800081e9b670 d sclk_core_pre_p
ffff800081e9b680 d apll_gpll_npll_p
ffff800081e9b698 d gpll_cpll_npll_vpll_p
ffff800081e9b6b8 d gpll_cpll_p
ffff800081e9b6c8 d cpll_gpll_p
ffff800081e9b6d8 d npll_gpll_p
ffff800081e9b6e8 d gpll_cpll_npll_p
ffff800081e9b700 d mpll_gpll_cpll_npll_p
ffff800081e9b720 d clk_rtc32k_pmu_p
ffff800081e9b738 d sclk_uart0_p
ffff800081e9b750 d sclk_uart9_p
ffff800081e9b768 d sclk_uart8_p
ffff800081e9b780 d sclk_uart7_p
ffff800081e9b798 d sclk_uart6_p
ffff800081e9b7b0 d sclk_uart5_p
ffff800081e9b7c8 d sclk_uart4_p
ffff800081e9b7e0 d sclk_uart3_p
ffff800081e9b7f8 d sclk_uart2_p
ffff800081e9b810 d sclk_uart1_p
ffff800081e9b828 d sclk_audpwm_p
ffff800081e9b838 d mclk_spdif_8ch_p
ffff800081e9b848 d clk_i2s3_2ch_rx_p
ffff800081e9b868 d clk_i2s3_2ch_tx_p
ffff800081e9b888 d clk_i2s2_2ch_p
ffff800081e9b8a8 d clk_i2s1_8ch_rx_p
ffff800081e9b8c8 d clk_i2s1_8ch_tx_p
ffff800081e9b8e8 d clk_i2s0_8ch_rx_p
ffff800081e9b908 d clk_i2s0_8ch_tx_p
ffff800081e9b928 d mux_usb480m_phy_p
ffff800081e9b938 d mux_usb480m_p
ffff800081e9b950 d mux_pll_p
ffff800081e9b958 d mux_armclkl_p
ffff800081e9b970 d mux_armclkb_p
ffff800081e9b988 d clk_aupll_ref_src_p
ffff800081e9b998 d clk_cpll_ref_src_p
ffff800081e9b9a8 d clk_usbphy_ref_src_p
ffff800081e9b9b8 d clk_phy_ref_src_p
ffff800081e9b9c8 d mux_pmu100m_24m_32k_p
ffff800081e9b9e0 d mux_pmu100m_pmu50m_24m_p
ffff800081e9b9f8 d mux_pmu200m_pmu100m_pmu50m_24m_p
ffff800081e9ba18 d clk_ref_osc_mphy_p
ffff800081e9ba30 d hclk_vi_root_p
ffff800081e9ba50 d clk_ref_pcie0_phy_p
ffff800081e9ba68 d sai_sclkin_freq_p
ffff800081e9ba90 d clk_counter_pwm1_p
ffff800081e9bac0 d clk_freq_pwm1_p
ffff800081e9baf0 d clk_uart_p
ffff800081e9bb28 d dclk_vp2_p
ffff800081e9bb38 d dclk_vp1_p
ffff800081e9bb48 d dclk_vp0_p
ffff800081e9bb58 d dclk_ebc_p
ffff800081e9bb90 d clk_gmac0_ptp_ref_src_p
ffff800081e9bba8 d clk_gmac1_ptp_ref_src_p
ffff800081e9bbc0 d uart1_p
ffff800081e9bbd0 d mclk_sai9_8ch_p
ffff800081e9bbe0 d mclk_sai8_8ch_p
ffff800081e9bbf0 d mclk_sai7_8ch_p
ffff800081e9bc00 d mclk_sai6_8ch_p
ffff800081e9bc10 d mclk_sai5_8ch_p
ffff800081e9bc20 d mclk_sai4_2ch_p
ffff800081e9bc38 d mclk_sai3_2ch_p
ffff800081e9bc50 d mclk_sai2_2ch_p
ffff800081e9bc68 d mclk_sai1_8ch_p
ffff800081e9bc78 d mclk_sai0_8ch_p
ffff800081e9bc90 d mux_116m_58m_24m_p
ffff800081e9bca8 d mux_175m_116m_58m_24m_p
ffff800081e9bcc8 d mux_350m_175m_116m_24m_p
ffff800081e9bce8 d mux_600m_400m_300m_24m_p
ffff800081e9bd08 d mux_500m_250m_100m_24m_p
ffff800081e9bd28 d mux_400m_200m_100m_24m_p
ffff800081e9bd48 d mux_200m_150m_100m_24m_p
ffff800081e9bd68 d mux_200m_100m_50m_24m_p
ffff800081e9bd88 d mux_150m_100m_50m_24m_p
ffff800081e9bda8 d mux_100m_24m_lclk1_p
ffff800081e9bdc0 d mux_100m_24m_lclk0_p
ffff800081e9bdd8 d mux_100m_50m_24m_p
ffff800081e9bdf0 d mux_100m_24m_p
ffff800081e9be00 d audio_frac_p
ffff800081e9be20 d audio_frac_int_p
ffff800081e9be60 d mux_24m_spll_gpll_cpll_p
ffff800081e9be80 d mux_24m_ccipvtpll_gpll_lpll_p
ffff800081e9bea0 d cpll_vpll_lpll_bpll_p
ffff800081e9bec0 d gpll_cpll_spll_vpll_bpll_lpll_p
ffff800081e9bef0 d gpll_cpll_spll_aupll_lpll_24m_p
ffff800081e9bf20 d gpll_spll_isppvtpll_bpll_lpll_p
ffff800081e9bf48 d gpll_spll_aupll_bpll_lpll_p
ffff800081e9bf70 d gpll_cpll_vpll_bpll_lpll_p
ffff800081e9bf98 d gpll_cpll_spll_lpll_bpll_p
ffff800081e9bfc0 d gpll_cpll_spll_bpll_lpll_p
ffff800081e9bfe8 d gpll_cpll_spll_aupll_bpll_p
ffff800081e9c010 d gpll_cpll_vpll_aupll_24m_p
ffff800081e9c038 d gpll_spll_cpll_bpll_lpll_p
ffff800081e9c060 d gpll_cpll_lpll_bpll_p
ffff800081e9c080 d gpll_cpll_spll_bpll_p
ffff800081e9c0a0 d gpll_cpll_aupll_spll_lpll_p
ffff800081e9c0c8 d gpll_cpll_aupll_spll_p
ffff800081e9c0e8 d gpll_cpll_aupll_24m_p
ffff800081e9c108 d gpll_cpll_24m_spll_p
ffff800081e9c128 d gpll_cpll_24m_p
ffff800081e9c140 d gpll_cpll_aupll_p
ffff800081e9c158 d gpll_spll_p
ffff800081e9c168 d gpll_cpll_p
ffff800081e9c178 d cpll_24m_p
ffff800081e9c188 d gpll_24m_p
ffff800081e9c198 d mux_24m_32k_p
ffff800081e9c1a8 d mux_pll_p
ffff800081e9c1b8 d mux_armclkl_p
ffff800081e9c1d0 d mux_armclkb01_p
ffff800081e9c1e8 d mux_armclkb23_p
ffff800081e9c200 d clk_ref_pipe_phy2_p
ffff800081e9c210 d clk_ref_pipe_phy1_p
ffff800081e9c220 d clk_ref_pipe_phy0_p
ffff800081e9c230 d mux_24m_ppll_p
ffff800081e9c240 d mux_24m_ppll_spll_p
ffff800081e9c258 d mclk_pdm0_p
ffff800081e9c268 d hclk_pmu_cm0_root_p
ffff800081e9c288 d hclk_pmu1_root_p
ffff800081e9c2a8 d pmu_24m_32k_100m_src_p
ffff800081e9c2c0 d pmu_100m_50m_24m_src_p
ffff800081e9c2d8 d pmu_400m_24m_p
ffff800081e9c2e8 d pmu_300m_24m_p
ffff800081e9c2f8 d pmu_200m_100m_p
ffff800081e9c308 d dclk_vop2_p
ffff800081e9c320 d dclk_vop1_p
ffff800081e9c338 d dclk_vop0_p
ffff800081e9c350 d aclk_vop_sub_src_p
ffff800081e9c360 d aclk_hdcp1_root_p
ffff800081e9c378 d clk_hdmirx_aud_p
ffff800081e9c388 d clk_gmac1_ptp_ref_p
ffff800081e9c398 d clk_gmac0_ptp_ref_p
ffff800081e9c3a8 d clk_uart9_p
ffff800081e9c3c0 d clk_uart8_p
ffff800081e9c3d8 d clk_uart7_p
ffff800081e9c3f0 d clk_uart6_p
ffff800081e9c408 d clk_uart5_p
ffff800081e9c420 d clk_uart4_p
ffff800081e9c438 d clk_uart3_p
ffff800081e9c450 d clk_uart2_p
ffff800081e9c468 d clk_uart1_p
ffff800081e9c480 d clk_uart0_p
ffff800081e9c498 d clk_spdif5_dp1_p
ffff800081e9c4b0 d clk_spdif4_p
ffff800081e9c4c8 d clk_spdif3_p
ffff800081e9c4e0 d clk_spdif2_dp0_p
ffff800081e9c4f8 d clk_spdif1_p
ffff800081e9c510 d clk_spdif0_p
ffff800081e9c528 d clk_i2s10_8ch_rx_p
ffff800081e9c548 d clk_i2s9_8ch_rx_p
ffff800081e9c568 d clk_i2s8_8ch_tx_p
ffff800081e9c588 d clk_i2s7_8ch_rx_p
ffff800081e9c5a8 d i2s6_8ch_mclkout_p
ffff800081e9c5c0 d clk_i2s6_8ch_rx_p
ffff800081e9c5e0 d clk_i2s6_8ch_tx_p
ffff800081e9c600 d clk_i2s5_8ch_tx_p
ffff800081e9c620 d clk_i2s4_8ch_tx_p
ffff800081e9c640 d i2s1_8ch_mclkout_p
ffff800081e9c658 d clk_i2s1_8ch_rx_p
ffff800081e9c678 d clk_i2s1_8ch_tx_p
ffff800081e9c698 d i2s0_8ch_mclkout_p
ffff800081e9c6b0 d clk_i2s0_8ch_rx_p
ffff800081e9c6d0 d clk_i2s0_8ch_tx_p
ffff800081e9c6f0 d i2s3_2ch_mclkout_p
ffff800081e9c700 d clk_i2s3_2ch_p
ffff800081e9c720 d i2s2_2ch_mclkout_p
ffff800081e9c730 d clk_i2s2_2ch_p
ffff800081e9c750 d mux_400m_200m_100m_24m_p
ffff800081e9c770 d mux_500m_300m_100m_24m_p
ffff800081e9c790 d mux_500m_250m_100m_24m_p
ffff800081e9c7b0 d mux_700m_400m_200m_24m_p
ffff800081e9c7d0 d mux_300m_200m_100m_24m_p
ffff800081e9c7f0 d mux_200m_100m_50m_24m_p
ffff800081e9c810 d mux_150m_100m_50m_24m_p
ffff800081e9c830 d mux_200m_150m_24m_p
ffff800081e9c848 d mux_150m_100m_24m_p
ffff800081e9c860 d mux_150m_50m_24m_p
ffff800081e9c878 d mux_100m_50m_24m_p
ffff800081e9c890 d mux_200m_100m_p
ffff800081e9c8a0 d mux_24m_100m_p
ffff800081e9c8b0 d mux_24m_32k_p
ffff800081e9c8c0 d mux_24m_spll_gpll_cpll_p
ffff800081e9c8e0 d gpll_cpll_npll_1000m_p
ffff800081e9c900 d gpll_cpll_npll_aupll_spll_p
ffff800081e9c928 d gpll_cpll_dmyaupll_npll_spll_p
ffff800081e9c950 d gpll_cpll_aupll_npll_spll_p
ffff800081e9c978 d gpll_cpll_v0pll_spll_p
ffff800081e9c998 d gpll_cpll_v0pll_aupll_p
ffff800081e9c9b8 d gpll_cpll_aupll_npll_p
ffff800081e9c9d8 d gpll_cpll_aupll_spll_p
ffff800081e9c9f8 d gpll_cpll_24m_spll_p
ffff800081e9ca18 d gpll_cpll_npll_v0pll_p
ffff800081e9ca38 d gpll_cpll_npll_p
ffff800081e9ca50 d gpll_cpll_aupll_p
ffff800081e9ca68 d gpll_cpll_24m_p
ffff800081e9ca80 d gpll_spll_p
ffff800081e9ca90 d gpll_cpll_p
ffff800081e9caa0 d gpll_lpll_p
ffff800081e9cab0 d gpll_aupll_p
ffff800081e9cac0 d gpll_24m_p
ffff800081e9cad0 d b0pll_b1pll_lpll_gpll_p
ffff800081e9caf0 d mux_pll_p
ffff800081e9cb00 d cmu_imem_info
ffff800081e9cba0 d cmu_peri_info
ffff800081e9cc40 d cmu_peri_gate_clks
ffff800081e9cf40 d cmu_peri_div_clks
ffff800081e9d0c8 d cmu_peri_mux_clks
ffff800081e9d1e0 d mout_peri_i2s1_p
ffff800081e9d1f0 d mout_peri_i2s0_p
ffff800081e9d200 d mout_peri_disp_user_p
ffff800081e9d210 d mout_peri_audio_user_p
ffff800081e9d220 d mout_peri_ip_user_p
ffff800081e9d230 d peri_fixed_clks
ffff800081e9d258 d cmu_peri_clk_regs
ffff800081e9d320 d cmu_imem_gate_clks
ffff800081e9d380 d cmu_imem_mux_clks
ffff800081e9d460 d mout_imem_jpeg_user_p
ffff800081e9d470 d mout_imem_gic_ca5_p
ffff800081e9d480 d mout_imem_gic_ca53_p
ffff800081e9d490 d mout_imem_aclk_user_p
ffff800081e9d4a0 d cmu_imem_clk_regs
ffff800081e9d4d0 d cmu_fsys_info
ffff800081e9d570 d cmu_fsys_gate_clks
ffff800081e9da20 d cmu_fsys_div_clks
ffff800081e9ddd8 d cmu_fsys_mux_clks
ffff800081e9def0 d mout_fsys_pll_fsys_p
ffff800081e9df00 d mout_fsys_mmc_user_p
ffff800081e9df10 d mout_fsys_bus_user_p
ffff800081e9df20 d mout_fsys_scan1_user_p
ffff800081e9df30 d mout_fsys_scan0_user_p
ffff800081e9df40 d cmu_fsys_pll_clks
ffff800081e9df78 d cmu_fsys_clk_regs
ffff800081e9e0e0 d cmu_cpucl_info
ffff800081e9e180 d cmu_cpucl_gate_clks
ffff800081e9e240 d cmu_cpucl_div_clks
ffff800081e9e400 d cpucl_ffactor_clks
ffff800081e9e430 d cmu_cpucl_mux_clks
ffff800081e9e4d8 d mout_clk_cpucl_pll_p
ffff800081e9e4e8 d mout_pll_cpucl_p
ffff800081e9e4f8 d mout_clkcmu_cpucl_switch_user_p
ffff800081e9e508 d cmu_cpucl_pll_clks
ffff800081e9e540 d cmu_cpucl_clk_regs
ffff800081e9e5b8 d cmu_core_info
ffff800081e9e658 d cmu_core_div_clks
ffff800081e9e690 d cmu_core_mux_clks
ffff800081e9e700 d mout_clk_core_dlp_user_p
ffff800081e9e710 d mout_clk_core_aclk_user_p
ffff800081e9e720 d cmu_core_clk_regs
ffff800081e9e738 d cmu_bus_info
ffff800081e9e7d8 d cmu_bus_div_clks
ffff800081e9e810 d cmu_bus_mux_clks
ffff800081e9e880 d mout_clk_bus_dlp_user_p
ffff800081e9e890 d mout_clk_bus_aclk_user_p
ffff800081e9e8a0 d cmu_bus_clk_regs
ffff800081e9e8b8 d cmu_cmu_info
ffff800081e9e958 d cmu_cmu_div_clks
ffff800081e9f100 d cmu_cmu_mux_clks
ffff800081e9f790 d cmu_fixed_factor_clks
ffff800081e9f7c0 d mout_clkcmu_pll_audio_p
ffff800081e9f7d0 d mout_clkcmu_pll_shared1_p
ffff800081e9f7e0 d mout_clkcmu_pll_shared0_p
ffff800081e9f7f0 d mout_clkcmu_vpp_core_p
ffff800081e9f810 d mout_clkcmu_vip1_core_p
ffff800081e9f830 d mout_clkcmu_vip0_core_p
ffff800081e9f850 d mout_clkcmu_vio_core_p
ffff800081e9f870 d mout_clkcmu_vca_od_p
ffff800081e9f890 d mout_clkcmu_vca_ace_p
ffff800081e9f8b0 d mout_clkcmu_trfm_core_p
ffff800081e9f8d0 d mout_clkcmu_rsp_core_p
ffff800081e9f8f0 d mout_clkcmu_peri_ip_p
ffff800081e9f910 d mout_clkcmu_peri_disp_p
ffff800081e9f930 d mout_clkcmu_mif_busp_p
ffff800081e9f950 d mout_clkcmu_mif_switch_p
ffff800081e9f970 d mout_clkcmu_2d_p
ffff800081e9f990 d mout_clkcmu_3d_p
ffff800081e9f9b0 d mout_clkcmu_dlp_core_p
ffff800081e9f9d0 d mout_clkcmu_cdc_core_p
ffff800081e9f9f0 d mout_clkcmu_imem_jpeg_p
ffff800081e9fa10 d mout_clkcmu_imem_imem_p
ffff800081e9fa30 d mout_clkcmu_fsys_scan1_p
ffff800081e9fa40 d mout_clkcmu_fsys_scan0_p
ffff800081e9fa50 d mout_clkcmu_fsys_ip_p
ffff800081e9fa70 d mout_clkcmu_fsys_bus_p
ffff800081e9fa90 d mout_clkcmu_cpucl_switch_p
ffff800081e9fab0 d mout_clkcmu_core_dlp_p
ffff800081e9fad0 d mout_clkcmu_core_bus_p
ffff800081e9faf0 d mout_clkcmu_bus_dlp_p
ffff800081e9fb10 d mout_clkcmu_bus_bus_p
ffff800081e9fb30 d cmu_cmu_pll_clks
ffff800081e9fbd8 d artpec8_pll_audio_rates
ffff800081e9fcb0 d cmu_cmu_clk_regs
ffff800081e9fed0 d atlas_cmu_info
ffff800081e9ff70 d apollo_cmu_info
ffff800081ea0010 d bus2_cmu_info
ffff800081ea00b0 d bus1_cmu_info
ffff800081ea0150 d bus0_cmu_info
ffff800081ea01f0 d peris_cmu_info
ffff800081ea0290 d peric_cmu_info
ffff800081ea0330 d mif_cmu_info
ffff800081ea03d0 d cpif_cmu_info
ffff800081ea0470 d top_cmu_info
ffff800081ea0510 d imem_cmu_info
ffff800081ea05b0 d imem_gate_clks
ffff800081ea0610 d imem_clk_regs
ffff800081ea0620 d cam1_cmu_info
ffff800081ea06c0 d cam1_gate_clks
ffff800081ea1740 d cam1_div_clks
ffff800081ea1970 d cam1_mux_clks
ffff800081ea1c48 d cam1_fixed_clks
ffff800081ea1c70 d mout_aclk_lite_c_a_p
ffff800081ea1c80 d mout_aclk_lite_c_b_p
ffff800081ea1c90 d mout_aclk_fd_a_p
ffff800081ea1ca0 d mout_aclk_fd_b_p
ffff800081ea1cb0 d mout_aclk_csis2_a_p
ffff800081ea1cc0 d mout_aclk_csis2_b_p
ffff800081ea1cd0 d mout_phyclk_rxbyteclkhs0_s2b_user_p
ffff800081ea1ce0 d mout_aclk_cam1_552_user_p
ffff800081ea1cf0 d mout_aclk_cam1_400_user_p
ffff800081ea1d00 d mout_aclk_cam1_333_user_p
ffff800081ea1d10 d mout_sclk_isp_spi0_user_p
ffff800081ea1d20 d mout_sclk_isp_spi1_user_p
ffff800081ea1d30 d mout_sclk_isp_uart_user_p
ffff800081ea1d40 d cam1_clk_regs
ffff800081ea1dc8 d cam0_cmu_info
ffff800081ea1e68 d cam0_gate_clks
ffff800081ea2e28 d cam0_div_clks
ffff800081ea3218 d cam0_mux_clks
ffff800081ea3800 d cam0_fixed_clks
ffff800081ea3850 d mout_sclk_pixelasync_lite_c_init_a_p
ffff800081ea3860 d mout_sclk_pixelasync_lite_c_init_b_p
ffff800081ea3870 d mout_sclk_pixelasync_lite_c_a_p
ffff800081ea3880 d mout_sclk_pixelasync_lite_c_b_p
ffff800081ea3890 d mout_sclk_lite_freecnt_a_p
ffff800081ea38a0 d mout_sclk_lite_freecnt_b_p
ffff800081ea38b0 d mout_sclk_lite_freecnt_c_p
ffff800081ea38c0 d mout_aclk_3aa0_a_p
ffff800081ea38d0 d mout_aclk_3aa0_b_p
ffff800081ea38e0 d mout_aclk_3aa1_a_p
ffff800081ea38f0 d mout_aclk_3aa1_b_p
ffff800081ea3900 d mout_aclk_csis0_a_p
ffff800081ea3910 d mout_aclk_csis0_b_p
ffff800081ea3920 d mout_aclk_csis1_a_p
ffff800081ea3930 d mout_aclk_csis1_b_p
ffff800081ea3940 d mout_aclk_cam0_400_p
ffff800081ea3950 d mout_aclk_lite_a_a_p
ffff800081ea3960 d mout_aclk_lite_a_b_p
ffff800081ea3970 d mout_aclk_lite_b_a_p
ffff800081ea3980 d mout_aclk_lite_b_b_p
ffff800081ea3990 d mout_aclk_lite_d_a_p
ffff800081ea39a0 d mout_aclk_lite_d_b_p
ffff800081ea39b0 d mout_phyclk_rxbyteclkhs0_s2a_user_p
ffff800081ea39c0 d mout_phyclk_rxbyteclkhs0_s4_user_p
ffff800081ea39d0 d mout_aclk_cam0_552_user_p
ffff800081ea39e0 d mout_aclk_cam0_400_user_p
ffff800081ea39f0 d mout_aclk_cam0_333_user_p
ffff800081ea3a00 d cam0_clk_regs
ffff800081ea3ac0 d isp_cmu_info
ffff800081ea3b60 d isp_gate_clks
ffff800081ea48b0 d isp_div_clks
ffff800081ea4990 d isp_mux_clks
ffff800081ea4a00 d mout_aclk_isp_400_user_p
ffff800081ea4a10 d mout_aclk_isp_dis_400_user_p
ffff800081ea4a20 d isp_clk_regs
ffff800081ea4a80 d hevc_cmu_info
ffff800081ea4b20 d hevc_gate_clks
ffff800081ea4e20 d hevc_div_clks
ffff800081ea4e58 d hevc_mux_clks
ffff800081ea4e90 d mout_aclk_hevc_400_user_p
ffff800081ea4ea0 d hevc_clk_regs
ffff800081ea4ef0 d mfc_cmu_info
ffff800081ea4f90 d mfc_gate_clks
ffff800081ea5290 d mfc_div_clks
ffff800081ea52c8 d mfc_mux_clks
ffff800081ea5300 d mout_aclk_mfc_400_user_p
ffff800081ea5310 d mfc_clk_regs
ffff800081ea5360 d mscl_cmu_info
ffff800081ea5400 d mscl_gate_clks
ffff800081ea58b0 d mscl_div_clks
ffff800081ea58e8 d mscl_mux_clks
ffff800081ea5990 d mout_sclk_jpeg_p
ffff800081ea59a0 d mout_aclk_mscl_400_user_p
ffff800081ea59b0 d mout_sclk_jpeg_user_p
ffff800081ea59c0 d mscl_clk_regs
ffff800081ea5a58 d atlas_cpu_clks
ffff800081ea5a88 d exynos5433_atlasclk_d
ffff800081ea5c08 d atlas_gate_clks
ffff800081ea6088 d atlas_div_clks
ffff800081ea6280 d atlas_mux_clks
ffff800081ea6328 d atlas_pll_clks
ffff800081ea6360 d mout_atlas_p
ffff800081ea6370 d mout_bus_pll_atlas_user_p
ffff800081ea6380 d mout_atlas_pll_p
ffff800081ea6390 d atlas_clk_regs
ffff800081ea6460 d apollo_cpu_clks
ffff800081ea6490 d exynos5433_apolloclk_d
ffff800081ea6598 d apollo_gate_clks
ffff800081ea67d8 d apollo_div_clks
ffff800081ea69d0 d apollo_mux_clks
ffff800081ea6a78 d apollo_pll_clks
ffff800081ea6ab0 d mout_apollo_p
ffff800081ea6ac0 d mout_bus_pll_apollo_user_p
ffff800081ea6ad0 d mout_apollo_pll_p
ffff800081ea6ae0 d apollo_clk_regs
ffff800081ea6bb0 d gscl_cmu_info
ffff800081ea6c50 d gscl_gate_clks
ffff800081ea7130 d gscl_mux_clks
ffff800081ea71a0 d aclk_gscl_333_user_p
ffff800081ea71b0 d aclk_gscl_111_user_p
ffff800081ea71c0 d gscl_clk_regs
ffff800081ea7238 d g3d_cmu_info
ffff800081ea72d8 d g3d_gate_clks
ffff800081ea7548 d g3d_div_clks
ffff800081ea75f0 d g3d_mux_clks
ffff800081ea7660 d g3d_pll_clks
ffff800081ea7698 d mout_g3d_pll_p
ffff800081ea76a8 d mout_aclk_g3d_400_p
ffff800081ea76b8 d g3d_clk_regs
ffff800081ea7738 d bus2_gate_clks
ffff800081ea7888 d bus2_div_clks
ffff800081ea78c0 d bus2_mux_clks
ffff800081ea78f8 d bus1_gate_clks
ffff800081ea7a18 d bus1_div_clks
ffff800081ea7a50 d bus0_gate_clks
ffff800081ea7b70 d bus0_div_clks
ffff800081ea7ba8 d bus2_clk_regs
ffff800081ea7be0 d bus01_clk_regs
ffff800081ea7c08 d mout_aclk_bus2_400_p
ffff800081ea7c18 d aud_cmu_info
ffff800081ea7cb8 d aud_gate_clks
ffff800081ea8258 d aud_div_clks
ffff800081ea8418 d aud_mux_clks
ffff800081ea84c0 d aud_fixed_clks
ffff800081ea8538 d mout_sclk_aud_pcm_p
ffff800081ea8548 d mout_aud_pll_user_aud_p
ffff800081ea8558 d aud_clk_regs
ffff800081ea85b8 d disp_cmu_info
ffff800081ea8658 d disp_gate_clks
ffff800081ea9348 d disp_div_clks
ffff800081ea94d0 d disp_mux_clks
ffff800081ea9a10 d disp_fixed_clks
ffff800081ea9b00 d disp_fixed_factor_clks
ffff800081ea9b60 d disp_pll_clks
ffff800081ea9b98 d mout_sclk_decon_tv_vclk_b_disp_p
ffff800081ea9ba8 d mout_sclk_decon_tv_vclk_c_disp_p
ffff800081ea9bb8 d mout_sclk_dsim1_b_disp_p
ffff800081ea9bc8 d mout_sclk_decon_eclk_p
ffff800081ea9bd8 d mout_sclk_decon_vclk_p
ffff800081ea9be8 d mout_sclk_decon_tv_eclk_p
ffff800081ea9bf8 d mout_sclk_dsim0_p
ffff800081ea9c08 d mout_phyclk_hdmiphy_pixel_clko_user_p
ffff800081ea9c18 d mout_phyclk_hdmiphy_tmds_clko_user_p
ffff800081ea9c28 d mout_phyclk_mipidphy0_rxclkesc0_user_p
ffff800081ea9c38 d mout_phyclk_mipidphy0_bitclkdiv8_user_p
ffff800081ea9c48 d mout_phyclk_mipidphy1_rxclkesc0_user_p
ffff800081ea9c58 d mout_phyclk_mipidphy1_bitclkdiv8_user_p
ffff800081ea9c68 d mout_aclk_disp_333_user_p
ffff800081ea9c78 d mout_sclk_decon_tv_vlkc_user_p
ffff800081ea9c88 d mout_sclk_decon_eclk_user_p
ffff800081ea9c98 d mout_sclk_decon_vclk_user_p
ffff800081ea9ca8 d mout_sclk_decon_tv_eclk_user_p
ffff800081ea9cb8 d mout_sclk_dsd_user_p
ffff800081ea9cc8 d mout_sclk_dsim0_user_p
ffff800081ea9cd8 d mout_sclk_dsim1_user_p
ffff800081ea9ce8 d mout_disp_pll_p
ffff800081ea9cf8 d disp_clk_regs
ffff800081ea9dc0 d g2d_cmu_info
ffff800081ea9e60 d g2d_gate_clks
ffff800081eaa2b0 d g2d_div_clks
ffff800081eaa2e8 d g2d_mux_clks
ffff800081eaa358 d mout_aclk_g2d_400_user_p
ffff800081eaa368 d mout_aclk_g2d_266_user_p
ffff800081eaa378 d g2d_clk_regs
ffff800081eaa3c8 d fsys_cmu_info
ffff800081eaa468 d fsys_gate_clks
ffff800081eab0c8 d fsys_mux_clks
ffff800081eab5d0 d fsys_fixed_clks
ffff800081eab7d8 d fsys_clk_regs
ffff800081eab868 d mout_sclk_mphy_p
ffff800081eab878 d mout_phyclk_lli_mphy_to_ufs_user_p
ffff800081eab888 d mout_phyclk_ufs_tx0_symbol_user_p
ffff800081eab898 d mout_phyclk_ufs_tx1_symbol_user_p
ffff800081eab8a8 d mout_phyclk_ufs_rx0_symbol_user_p
ffff800081eab8b8 d mout_phyclk_ufs_rx1_symbol_user_p
ffff800081eab8c8 d mout_phyclk_usbdrd30_udrd30_phyclock_user_p
ffff800081eab8d8 d mout_phyclk_usbdrd30_udrd30_pipe_pclk_p
ffff800081eab8e8 d mout_phyclk_usbhost20_phy_freeclk_user_p
ffff800081eab8f8 d mout_phyclk_usbhost20_phy_phyclock_user_p
ffff800081eab908 d mout_phyclk_usbhost20_phy_clk48mohci_user_p
ffff800081eab918 d mout_phyclk_usbhost20_phy_hsic1_p
ffff800081eab928 d mout_phyclk_usbhost30_uhost30_phyclock_user_p
ffff800081eab938 d mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p
ffff800081eab948 d mout_sclk_usbdrd30_user_p
ffff800081eab958 d mout_sclk_usbhost30_user_p
ffff800081eab968 d mout_sclk_mmc0_user_p
ffff800081eab978 d mout_sclk_mmc1_user_p
ffff800081eab988 d mout_sclk_mmc2_user_p
ffff800081eab998 d mout_sclk_ufsunipro_user_p
ffff800081eab9a8 d mout_sclk_pcie_100_user_p
ffff800081eab9b8 d mout_aclk_fsys_200_user_p
ffff800081eab9c8 d mout_sclk_ufs_mphy_user_p
ffff800081eab9d8 d peris_gate_clks
ffff800081eac188 d peris_clk_regs
ffff800081eac250 d peric_gate_clks
ffff800081eace80 d peric_div_clks
ffff800081eacef0 d peric_clk_regs
ffff800081eacf30 d mif_gate_clks
ffff800081eae2e0 d mif_div_clks
ffff800081eae778 d mif_mux_clks
ffff800081eaf000 d mif_fixed_factor_clks
ffff800081eaf0c0 d mout_sclk_dsim1_b_p
ffff800081eaf0d0 d mout_sclk_dsim1_c_p
ffff800081eaf0e0 d mout_sclk_decon_tv_vclk_b_p
ffff800081eaf0f0 d mout_sclk_decon_tv_vclk_c_p
ffff800081eaf100 d mout_sclk_dsim0_b_p
ffff800081eaf110 d mout_sclk_dsim0_c_p
ffff800081eaf120 d mout_sclk_dsd_a_p
ffff800081eaf130 d mout_sclk_dsd_b_p
ffff800081eaf140 d mout_sclk_dsd_c_p
ffff800081eaf150 d mout_sclk_decon_tv_eclk_b_p
ffff800081eaf160 d mout_sclk_decon_tv_eclk_c_p
ffff800081eaf170 d mout_sclk_decon_eclk_b_p
ffff800081eaf180 d mout_sclk_decon_eclk_c_p
ffff800081eaf190 d mout_sclk_decon_p
ffff800081eaf1a0 d mout_sclk_decon_vclk_b_p
ffff800081eaf1b0 d mout_sclk_decon_vclk_c_p
ffff800081eaf1c0 d mout_aclk_disp_333_a_p
ffff800081eaf1d0 d mout_aclk_disp_333_b_p
ffff800081eaf1e0 d mout_aclk_mifnm_400_p
ffff800081eaf1f0 d mout_aclk_mifnm_200_p
ffff800081eaf200 d mout_clkm_phy_b_p
ffff800081eaf210 d mout_clk2x_phy_a_p
ffff800081eaf220 d mout_clk2x_phy_b_p
ffff800081eaf230 d mout_clk2x_phy_c_p
ffff800081eaf240 d mout_mem0_pll_p
ffff800081eaf250 d mout_mem1_pll_p
ffff800081eaf260 d mout_bus_pll_p
ffff800081eaf270 d mout_mfc_pll_p
ffff800081eaf280 d mout_mem0_pll_div2_p
ffff800081eaf290 d mout_mem1_pll_div2_p
ffff800081eaf2a0 d mout_bus_pll_div2_p
ffff800081eaf2b0 d mout_mfc_pll_div2_p
ffff800081eaf2c0 d mif_pll_clks
ffff800081eaf3a0 d mif_clk_regs
ffff800081eaf590 d cpif_gate_clks
ffff800081eaf5f0 d cpif_div_clks
ffff800081eaf628 d cpif_mux_clks
ffff800081eaf660 d cpif_pll_clks
ffff800081eaf698 d mout_mphy_pll_p
ffff800081eaf6a8 d cpif_clk_regs
ffff800081eaf6e0 d top_pll_clks
ffff800081eaf750 d exynos5433_aud_pll_rates
ffff800081eaf8e0 d exynos5433_pll_rates
ffff800081eaffc8 d top_gate_clks
ffff800081eb09e8 d top_div_clks
ffff800081eb1820 d top_mux_clks
ffff800081eb2428 d top_fixed_clks
ffff800081eb2590 d top_fixed_factor_clks
ffff800081eb25c0 d mout_sclk_hdmi_spdif_p
ffff800081eb25d0 d mout_sclk_audio0_p
ffff800081eb25e8 d mout_sclk_audio1_p
ffff800081eb2600 d mout_sclk_spdif_p
ffff800081eb2620 d mout_sclk_mmc0_b_p
ffff800081eb2630 d mout_sclk_mmc0_c_p
ffff800081eb2640 d mout_sclk_mmc0_d_p
ffff800081eb2650 d mout_sclk_mmc1_b_p
ffff800081eb2660 d mout_sclk_mmc2_b_p
ffff800081eb2670 d mout_sclk_jpeg_b_p
ffff800081eb2680 d mout_sclk_jpeg_c_p
ffff800081eb2690 d mout_aclk_g2d_400_b_p
ffff800081eb26a0 d mout_aclk_mscl_b_p
ffff800081eb26b0 d mout_bus_mphy_pll_user_p
ffff800081eb26c0 d mout_aclk_mfc_400_a_p
ffff800081eb26d0 d mout_aclk_mfc_400_b_p
ffff800081eb26e0 d mout_aclk_mfc_400_c_p
ffff800081eb26f0 d mout_aclk_cam1_552_a_p
ffff800081eb2700 d mout_aclk_cam1_552_b_p
ffff800081eb2710 d mout_mfc_bus_pll_user_p
ffff800081eb2720 d mout_bus_mfc_pll_user_p
ffff800081eb2730 d mout_mphy_pll_user_t_p
ffff800081eb2740 d mout_bus_pll_user_t_p
ffff800081eb2750 d mout_bus_pll_user_p
ffff800081eb2760 d mout_mfc_pll_user_p
ffff800081eb2770 d mout_mphy_pll_user_p
ffff800081eb2780 d mout_aud_pll_user_p
ffff800081eb2790 d mout_isp_pll_p
ffff800081eb27a0 d mout_aud_pll_p
ffff800081eb27b0 d top_clk_regs
ffff800081eb2990 d peris_cmu_info
ffff800081eb2a30 d alive_cmu_info
ffff800081eb2ad0 d top_cmu_info
ffff800081eb2b70 d vts_cmu_info
ffff800081eb2c10 d vts_fixed_clks
ffff800081eb2c88 d vts_div_clks
ffff800081eb2e48 d vts_mux_clks
ffff800081eb2f98 d mout_clkvts_dmic_pad_p
ffff800081eb2fa8 d mout_clkvts_noc_p
ffff800081eb2fb8 d mout_clkvts_aud_dmic1_p
ffff800081eb2ff8 d mout_clkcmu_vts_dmic_user_p
ffff800081eb3008 d mout_clkalive_vts_rco_user_p
ffff800081eb3010 d mout_clkalive_vts_noc_user_p
ffff800081eb3018 d vts_clk_regs
ffff800081eb3258 d ufs_cmu_info
ffff800081eb32f8 d ufs_mux_clks
ffff800081eb33a0 d mout_clkcmu_ufs_ufs_embd_user_p
ffff800081eb33b0 d mout_clkcmu_ufs_noc_user_p
ffff800081eb33c0 d mout_clkcmu_ufs_mmc_card_user_p
ffff800081eb33d0 d ufs_clk_regs
ffff800081eb34e0 d peric2_cmu_info
ffff800081eb3580 d peric2_div_clks
ffff800081eb3820 d peric2_mux_clks
ffff800081eb3b68 d mout_peric2_usi11_p
ffff800081eb3b88 d mout_peric2_usi06_p
ffff800081eb3ba8 d mout_peric2_usi05_p
ffff800081eb3bc8 d mout_peric2_usi03_p
ffff800081eb3be8 d mout_peric2_usi02_p
ffff800081eb3c08 d mout_peric2_usi01_spi_i2c_p
ffff800081eb3c28 d mout_peric2_usi01_p
ffff800081eb3c48 d mout_peric2_usi00_spi_i2c_p
ffff800081eb3c68 d mout_peric2_usi00_p
ffff800081eb3c88 d mout_peric2_uart_dbg_p
ffff800081eb3ca8 d mout_peric2_spi_ms_ctrl_p
ffff800081eb3cc8 d mout_peric2_i2c_p
ffff800081eb3ce8 d mout_peric2_noc_user_p
ffff800081eb3cf8 d mout_peric2_ip1_user_p
ffff800081eb3d08 d mout_peric2_ip0_user_p
ffff800081eb3d18 d peric2_clk_regs
ffff800081eb4050 d peric1_cmu_info
ffff800081eb40f0 d peric1_div_clks
ffff800081eb42e8 d peric1_mux_clks
ffff800081eb4588 d mout_peric1_usi10_p
ffff800081eb45a8 d mout_peric1_usi09_p
ffff800081eb45c8 d mout_peric1_usi08_spi_i2c_p
ffff800081eb45e8 d mout_peric1_usi08_p
ffff800081eb4608 d mout_peric1_usi07_spi_i2c_p
ffff800081eb4628 d mout_peric1_usi07_p
ffff800081eb4648 d mout_peric1_uart_bt_p
ffff800081eb4668 d mout_peric1_spi_ms_ctrl_p
ffff800081eb4688 d mout_peric1_i2c_p
ffff800081eb46a8 d mout_peric1_noc_user_p
ffff800081eb46b8 d mout_peric1_ip1_user_p
ffff800081eb46c8 d mout_peric1_ip0_user_p
ffff800081eb46d8 d peric1_clk_regs
ffff800081eb48c0 d peric0_cmu_info
ffff800081eb4960 d peric0_div_clks
ffff800081eb49d0 d peric0_mux_clks
ffff800081eb4ae8 d mout_peric0_usi04_p
ffff800081eb4b08 d mout_peric0_i2c_p
ffff800081eb4b28 d mout_peric0_noc_user_p
ffff800081eb4b38 d mout_peric0_ip1_user_p
ffff800081eb4b48 d mout_peric0_ip0_user_p
ffff800081eb4b58 d peric0_clk_regs
ffff800081eb4c50 d hsi0_cmu_info
ffff800081eb4cf0 d hsi0_div_clks
ffff800081eb4d28 d hsi0_mux_clks
ffff800081eb4eb0 d mout_mux_clk_hsi0_usb32drd_p
ffff800081eb4ec0 d mout_mux_clk_hsi0_rtcclk_p
ffff800081eb4ed0 d mout_mux_clk_hsi0_noc_p
ffff800081eb4ed8 d mout_clkcmu_hsi0_usb32drd_user_p
ffff800081eb4ee8 d mout_clkcmu_hsi0_noc_user_p
ffff800081eb4ef8 d mout_clkcmu_hsi0_dposc_user_p
ffff800081eb4f08 d mout_clkcmu_hsi0_dpgtc_user_p
ffff800081eb4f18 d hsi0_clk_regs
ffff800081eb5090 d cmgp_cmu_info
ffff800081eb5130 d cmgp_div_clks
ffff800081eb5398 d cmgp_mux_clks
ffff800081eb5670 d mout_cmgp_usi6_p
ffff800081eb5680 d mout_cmgp_usi5_p
ffff800081eb5690 d mout_cmgp_usi4_p
ffff800081eb56a0 d mout_cmgp_usi3_p
ffff800081eb56b0 d mout_cmgp_usi2_p
ffff800081eb56c0 d mout_cmgp_usi1_p
ffff800081eb56d0 d mout_cmgp_usi0_p
ffff800081eb56e0 d mout_cmgp_spi_ms_ctrl_p
ffff800081eb56f0 d mout_cmgp_spi_i2c1_p
ffff800081eb5700 d mout_cmgp_spi_i2c0_p
ffff800081eb5710 d mout_cmgp_i2c_p
ffff800081eb5720 d mout_cmgp_clkalive_peri_user_p
ffff800081eb5730 d mout_cmgp_clkalive_noc_user_p
ffff800081eb5740 d cmgp_clk_regs
ffff800081eb59d0 d peris_fixed_factor_clks
ffff800081eb5a30 d peris_mux_clks
ffff800081eb5ad8 d mout_peris_gic_p
ffff800081eb5ae8 d mout_peris_noc_user_p
ffff800081eb5af8 d mout_peris_gic_user_p
ffff800081eb5b08 d peris_clk_regs
ffff800081eb5c18 d alive_fixed_clks
ffff800081eb5c90 d alive_div_clks
ffff800081eb5fd8 d alive_mux_clks
ffff800081eb6438 d mout_alive_dsp_noc_p
ffff800081eb6458 d mout_alive_csis_noc_p
ffff800081eb6478 d mout_alive_timer_p
ffff800081eb6488 d mout_alive_spmi_p
ffff800081eb64a8 d mout_alive_pmu_sub_p
ffff800081eb64c8 d mout_alive_noc_p
ffff800081eb64e8 d mout_alive_dbgcore_uart_p
ffff800081eb6508 d mout_alive_ufd_noc_p
ffff800081eb6528 d mout_alive_sdma_noc_p
ffff800081eb6548 d mout_alive_gnss_noc_p
ffff800081eb6558 d mout_alive_gnpu_noc_p
ffff800081eb6578 d mout_alive_chubvts_noc_p
ffff800081eb6598 d mout_alive_dnc_noc_p
ffff800081eb65b8 d mout_alive_dbgcore_noc_p
ffff800081eb65d8 d mout_alive_cmgp_peri_p
ffff800081eb65f8 d mout_alive_cmgp_noc_p
ffff800081eb6618 d mout_alive_chub_peri_p
ffff800081eb6638 d mout_rco_alive_user_p
ffff800081eb6648 d mout_alive_rco_spmi_user_p
ffff800081eb6658 d mout_alive_noc_user_p
ffff800081eb6668 d alive_clk_regs
ffff800081eb6a78 d top_fixed_factor_clks
ffff800081eb6ec8 d top_div_clks
ffff800081eb85f8 d top_mux_clks
ffff800081eb9e78 d top_pll_clks
ffff800081eba000 d mout_cmu_mux_ufs_noc_p
ffff800081eba020 d mout_cmu_mux_m2m_frc_p
ffff800081eba060 d mout_cmu_mcsc_noc_p
ffff800081eba0a0 d mout_cmu_mcsc_mcsc_p
ffff800081eba0e0 d mout_cmu_m2m_frc_p
ffff800081eba120 d mout_cmu_mux_cp_shared2_clk_p
ffff800081eba140 d mout_cmu_mux_cp_shared1_clk_p
ffff800081eba160 d mout_cmu_mux_cp_shared0_clk_p
ffff800081eba180 d mout_cmu_mux_cp_hispeedy_clk_p
ffff800081eba190 d mout_cmu_mux_cmu_cmuref_p
ffff800081eba1a0 d mout_cmu_mux_yuvp_noc_p
ffff800081eba1e0 d mout_cmu_mux_vts_dmic_p
ffff800081eba200 d mout_cmu_mux_ssp_noc_p
ffff800081eba220 d mout_cmu_mux_sdma_noc_p
ffff800081eba260 d mout_cmu_mux_peris_noc_p
ffff800081eba270 d mout_cmu_mux_peris_gic_p
ffff800081eba280 d mout_cmu_mux_peric2_noc_p
ffff800081eba290 d mout_cmu_mux_peric2_ip1_p
ffff800081eba2b0 d mout_cmu_mux_peric2_ip0_p
ffff800081eba2d0 d mout_cmu_mux_peric1_noc_p
ffff800081eba2e0 d mout_cmu_mux_peric1_ip1_p
ffff800081eba300 d mout_cmu_mux_peric1_ip0_p
ffff800081eba320 d mout_cmu_mux_peric0_noc_p
ffff800081eba330 d mout_cmu_mux_peric0_ip1_p
ffff800081eba350 d mout_cmu_mux_peric0_ip0_p
ffff800081eba370 d mout_cmu_mux_nocl1c_noc_p
ffff800081eba3b0 d mout_cmu_mux_nocl1b_noc1_p
ffff800081eba3d0 d mout_cmu_mux_nocl1b_noc0_p
ffff800081eba410 d mout_cmu_mux_nocl1a_noc_p
ffff800081eba450 d mout_cmu_mux_nocl0_noc_p
ffff800081eba490 d mout_cmu_mux_mif_switch_p
ffff800081eba4d0 d mout_cmu_mux_mif_nocp_p
ffff800081eba4f0 d mout_cmu_mux_mfc1_mfc1_p
ffff800081eba530 d mout_cmu_mux_mfc0_wfd_p
ffff800081eba570 d mout_cmu_mux_mfc0_mfc0_p
ffff800081eba5b0 d mout_cmu_mux_mcsc_noc_p
ffff800081eba5f0 d mout_cmu_mux_mcsc_mcsc_p
ffff800081eba630 d mout_cmu_mux_m2m_noc_p
ffff800081eba670 d mout_cmu_mux_lme_noc_p
ffff800081eba6b0 d mout_cmu_mux_lme_lme_p
ffff800081eba6f0 d mout_cmu_mux_ufs_ufs_embd_p
ffff800081eba710 d mout_cmu_mux_hsi1_pcie_p
ffff800081eba720 d mout_cmu_mux_hsi1_noc_p
ffff800081eba740 d mout_cmu_mux_ufs_mmc_card_p
ffff800081eba760 d mout_cmu_mux_hsi0_usb32drd_p
ffff800081eba780 d mout_cmu_mux_hsi0_noc_p
ffff800081eba7a0 d mout_cmu_mux_hsi0_dposc_p
ffff800081eba7b0 d mout_cmu_mux_hsi0_dpgtc_p
ffff800081eba7d0 d mout_cmu_mux_gnpu_noc_p
ffff800081eba810 d mout_cmu_mux_g3d_switch_p
ffff800081eba850 d mout_cmu_mux_g3d_nocp_p
ffff800081eba870 d mout_cmu_mux_dsu_switch_p
ffff800081eba8b0 d mout_cmu_mux_dsp_noc_p
ffff800081eba8f0 d mout_cmu_mux_dpuf_alt_p
ffff800081eba930 d mout_cmu_mux_dpuf_p
ffff800081eba970 d mout_cmu_mux_dpub_dsim_p
ffff800081eba990 d mout_cmu_mux_dpub_alt_p
ffff800081eba9d0 d mout_cmu_mux_dpub_p
ffff800081ebaa10 d mout_cmu_mux_dnc_noc_p
ffff800081ebaa50 d mout_cmu_mux_cstat_noc_p
ffff800081ebaa90 d mout_cmu_mux_csis_ois_mcu_p
ffff800081ebaaa0 d mout_cmu_mux_csis_noc_p
ffff800081ebaae0 d mout_cmu_mux_csis_dcphy_p
ffff800081ebab00 d mout_cmu_mux_cpucl2_switch_p
ffff800081ebab40 d mout_cmu_mux_cpucl1_switch_p
ffff800081ebab80 d mout_cmu_mux_cpucl0_switch_p
ffff800081ebabc0 d mout_cmu_mux_cpucl0_nocp_p
ffff800081ebabe0 d mout_cmu_mux_cpucl0_dbg_noc_p
ffff800081ebac00 d mout_cmu_mux_cmu_boost_mif_p
ffff800081ebac20 d mout_cmu_mux_cmu_boost_cpu_p
ffff800081ebac40 d mout_cmu_mux_cmu_boost_cam_p
ffff800081ebac60 d mout_cmu_mux_cmu_boost_p
ffff800081ebac80 d mout_cmu_mux_cis_clk7_p
ffff800081ebac90 d mout_cmu_mux_cis_clk6_p
ffff800081ebaca0 d mout_cmu_mux_cis_clk5_p
ffff800081ebacb0 d mout_cmu_mux_cis_clk4_p
ffff800081ebacc0 d mout_cmu_mux_cis_clk3_p
ffff800081ebacd0 d mout_cmu_mux_cis_clk2_p
ffff800081ebace0 d mout_cmu_mux_cis_clk1_p
ffff800081ebacf0 d mout_cmu_mux_cis_clk0_p
ffff800081ebad00 d mout_cmu_mux_brp_noc_p
ffff800081ebad40 d mout_cmu_mux_aud_noc_p
ffff800081ebad80 d mout_cmu_mux_aud_cpu_p
ffff800081ebadc0 d mout_cmu_mux_aud_audif1_p
ffff800081ebae00 d mout_cmu_mux_aud_audif0_p
ffff800081ebae40 d mout_cmu_mux_alive_noc_p
ffff800081ebae50 d mout_cmu_cp_shared2_clk_p
ffff800081ebae70 d mout_cmu_cp_shared0_clk_p
ffff800081ebae90 d mout_cmu_cp_hispeedy_clk_p
ffff800081ebaea0 d mout_cmu_sdma_noc_p
ffff800081ebaee0 d mout_cmu_nocl1c_noc_p
ffff800081ebaf20 d mout_cmu_nocl1b_noc0_p
ffff800081ebaf60 d mout_cmu_nocl1a_noc_p
ffff800081ebafa0 d mout_cmu_nocl0_noc_p
ffff800081ebafe0 d mout_cmu_m2m_noc_p
ffff800081ebb020 d mout_cmu_ufs_mmc_card_p
ffff800081ebb040 d mout_cmu_gnpu_noc_p
ffff800081ebb080 d mout_cmu_g3d_switch_p
ffff800081ebb0c0 d mout_cmu_dsu_switch_p
ffff800081ebb100 d mout_cmu_dsp_noc_p
ffff800081ebb140 d mout_cmu_dpuf_noc_p
ffff800081ebb150 d mout_cmu_dpub_noc_p
ffff800081ebb160 d mout_cmu_dnc_noc_p
ffff800081ebb1a0 d mout_cmu_cpucl2_switch_p
ffff800081ebb1e0 d mout_cmu_cpucl1_switch_p
ffff800081ebb220 d mout_cmu_cpucl0_switch_p
ffff800081ebb260 d mout_cmu_cpucl0_dbg_noc_p
ffff800081ebb280 d mout_cmu_aud_cpu_p
ffff800081ebb2c0 d mout_cmu_aud_audif1_p
ffff800081ebb300 d mout_cmu_aud_audif0_p
ffff800081ebb340 d mout_cmu_cp_mpll_clk_user_parents
ffff800081ebb348 d mout_cmu_cp_mpll_clk_d2_user_parents
ffff800081ebb350 d top_clk_regs
ffff800081ebbe38 d aud_cmu_info
ffff800081ebbed8 d mscl_cmu_info
ffff800081ebbf78 d fsys1_cmu_info
ffff800081ebc018 d fsys0_cmu_info
ffff800081ebc0b8 d peris_cmu_info
ffff800081ebc158 d peric1_cmu_info
ffff800081ebc1f8 d peric0_cmu_info
ffff800081ebc298 d ccore_cmu_info
ffff800081ebc338 d top1_cmu_info
ffff800081ebc3d8 d top0_cmu_info
ffff800081ebc478 d topc_cmu_info
ffff800081ebc518 d aud_gate_clks
ffff800081ebc848 d aud_div_clks
ffff800081ebca08 d aud_mux_clks
ffff800081ebcab0 d aud_clk_regs
ffff800081ebcae0 d mout_aud_group_p
ffff800081ebcaf0 d mout_aud_pll_user_p
ffff800081ebcb00 d mscl_gate_clks
ffff800081ebd0a0 d mscl_div_clks
ffff800081ebd0d8 d mscl_mux_clks
ffff800081ebd110 d mscl_clk_regs
ffff800081ebd130 d mout_aclk_mscl_532_user_p
ffff800081ebd140 d fsys1_gate_clks
ffff800081ebd320 d fsys1_div_clks
ffff800081ebd358 d fsys1_mux_clks
ffff800081ebd550 d fsys1_clk_regs
ffff800081ebd598 d fixed_rate_clks_fsys1
ffff800081ebd610 d mout_phyclk_ufs20_rx1_user_p
ffff800081ebd620 d mout_phyclk_ufs20_rx0_user_p
ffff800081ebd630 d mout_phyclk_ufs20_tx0_user_p
ffff800081ebd640 d mout_sclk_ufsunipro20_user_p
ffff800081ebd650 d mout_sclk_mmc1_user_p
ffff800081ebd660 d mout_sclk_mmc0_user_p
ffff800081ebd670 d mout_fsys1_group_p
ffff800081ebd688 d mout_aclk_fsys1_200_user_p
ffff800081ebd698 d fsys0_gate_clks
ffff800081ebd878 d fsys0_mux_clks
ffff800081ebd990 d fsys0_clk_regs
ffff800081ebd9d0 d fixed_rate_clks_fsys0
ffff800081ebda20 d mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p
ffff800081ebda30 d mout_phyclk_usbdrd300_udrd30_phyclk_user_p
ffff800081ebda40 d mout_sclk_usbdrd300_user_p
ffff800081ebda50 d mout_sclk_mmc2_user_p
ffff800081ebda60 d mout_aclk_fsys0_200_user_p
ffff800081ebda70 d peris_gate_clks
ffff800081ebdb60 d peris_mux_clks
ffff800081ebdb98 d peris_clk_regs
ffff800081ebdbc0 d mout_aclk_peris_66_user_p
ffff800081ebdbd0 d peric1_gate_clks
ffff800081ebe0e0 d peric1_mux_clks
ffff800081ebe2d8 d peric1_clk_regs
ffff800081ebe300 d mout_sclk_spi4_user_p
ffff800081ebe310 d mout_sclk_spi3_user_p
ffff800081ebe320 d mout_sclk_spi2_user_p
ffff800081ebe330 d mout_sclk_spi1_user_p
ffff800081ebe340 d mout_sclk_spi0_user_p
ffff800081ebe350 d mout_sclk_uart3_user_p
ffff800081ebe360 d mout_sclk_uart2_user_p
ffff800081ebe370 d mout_sclk_uart1_user_p
ffff800081ebe380 d mout_aclk_peric1_66_user_p
ffff800081ebe390 d peric0_gate_clks
ffff800081ebe5d0 d peric0_mux_clks
ffff800081ebe640 d peric0_clk_regs
ffff800081ebe658 d mout_sclk_uart0_user_p
ffff800081ebe668 d mout_aclk_peric0_66_user_p
ffff800081ebe678 d ccore_gate_clks
ffff800081ebe6a8 d ccore_mux_clks
ffff800081ebe6e0 d ccore_clk_regs
ffff800081ebe6f0 d mout_aclk_ccore_133_user_p
ffff800081ebe700 d top1_fixed_factor_clks
ffff800081ebe7c0 d top1_gate_clks
ffff800081ebe970 d top1_div_clks
ffff800081ebeb68 d top1_mux_clks
ffff800081ebef58 d top1_clk_regs
ffff800081ebefc8 d mout_top1_group1
ffff800081ebefe8 d mout_top1_mfc_pll_half_p
ffff800081ebeff8 d mout_top1_cc_pll_half_p
ffff800081ebf008 d mout_top1_bus1_pll_half_p
ffff800081ebf018 d mout_top1_bus0_pll_half_p
ffff800081ebf028 d mout_top1_mfc_pll_user_p
ffff800081ebf038 d mout_top1_cc_pll_user_p
ffff800081ebf048 d mout_top1_bus1_pll_user_p
ffff800081ebf058 d mout_top1_bus0_pll_user_p
ffff800081ebf068 d top0_fixed_factor_clks
ffff800081ebf128 d top0_gate_clks
ffff800081ebf3c8 d top0_div_clks
ffff800081ebf6d8 d top0_mux_clks
ffff800081ebfbe0 d top0_clk_regs
ffff800081ebfc60 d mout_top0_group4
ffff800081ebfc80 d mout_top0_group3
ffff800081ebfcb0 d mout_top0_group1
ffff800081ebfcd0 d mout_top0_mfc_pll_half_p
ffff800081ebfce0 d mout_top0_cc_pll_half_p
ffff800081ebfcf0 d mout_top0_bus1_pll_half_p
ffff800081ebfd00 d mout_top0_bus0_pll_half_p
ffff800081ebfd10 d mout_top0_aud_pll_user_p
ffff800081ebfd20 d mout_top0_mfc_pll_user_p
ffff800081ebfd30 d mout_top0_cc_pll_user_p
ffff800081ebfd40 d mout_top0_bus1_pll_user_p
ffff800081ebfd50 d mout_top0_bus0_pll_user_p
ffff800081ebfd60 d topc_pll_clks
ffff800081ebfe78 d topc_gate_clks
ffff800081ec00b8 d pll1460x_24mhz_tbl
ffff800081ec0100 d topc_div_clks
ffff800081ec02c0 d topc_mux_clks
ffff800081ec0598 d topc_clk_regs
ffff800081ec0620 d mout_topc_bus0_pll_out_p
ffff800081ec0630 d mout_topc_mfc_pll_half_p
ffff800081ec0640 d mout_topc_cc_pll_half_p
ffff800081ec0650 d mout_topc_bus1_pll_half_p
ffff800081ec0660 d mout_topc_bus0_pll_half_p
ffff800081ec0678 d mout_topc_group2
ffff800081ec0698 d mout_topc_mfc_pll_ctrl_p
ffff800081ec06a8 d mout_topc_cc_pll_ctrl_p
ffff800081ec06b8 d mout_topc_bus1_pll_ctrl_p
ffff800081ec06c8 d mout_topc_bus0_pll_ctrl_p
ffff800081ec06d8 d mout_topc_aud_pll_ctrl_p
ffff800081ec06e8 d topc_fixed_factor_clks
ffff800081ec07d8 d peri_cmu_info
ffff800081ec0878 d peri_gate_clks
ffff800081ec1148 d peri_clk_regs
ffff800081ec12c0 d mfcmscl_cmu_info
ffff800081ec1360 d mfcmscl_gate_clks
ffff800081ec1510 d mfcmscl_div_clks
ffff800081ec1548 d mfcmscl_mux_clks
ffff800081ec15b8 d mout_mfcmscl_mscl_user_p
ffff800081ec15c8 d mout_mfcmscl_mfc_user_p
ffff800081ec15d8 d mfcmscl_clk_regs
ffff800081ec1638 d isp_cmu_info
ffff800081ec16d8 d isp_gate_clks
ffff800081ec1a38 d isp_div_clks
ffff800081ec1aa8 d isp_mux_clks
ffff800081ec1c30 d mout_isp_vra_p
ffff800081ec1c40 d mout_isp_ispd_p
ffff800081ec1c50 d mout_isp_isp_p
ffff800081ec1c60 d mout_isp_cam_p
ffff800081ec1c70 d mout_isp_vra_user_p
ffff800081ec1c80 d mout_isp_user_p
ffff800081ec1c90 d mout_isp_cam_user_p
ffff800081ec1ca0 d isp_pll_clks
ffff800081ec1cd8 d isp_fixed_clks
ffff800081ec1d28 d isp_clk_regs
ffff800081ec1e10 d g3d_cmu_info
ffff800081ec1eb0 d g3d_gate_clks
ffff800081ec20f0 d g3d_div_clks
ffff800081ec2160 d g3d_mux_clks
ffff800081ec21d0 d mout_g3d_p
ffff800081ec21e0 d mout_g3d_switch_user_p
ffff800081ec21f0 d g3d_pll_clks
ffff800081ec2228 d g3d_clk_regs
ffff800081ec22b8 d fsys_cmu_info
ffff800081ec2358 d fsys_gate_clks
ffff800081ec2658 d fsys_pll_clks
ffff800081ec2690 d fsys_fixed_clks
ffff800081ec26b8 d fsys_clk_regs
ffff800081ec2748 d dispaud_cmu_info
ffff800081ec27e8 d dispaud_gate_clks
ffff800081ec2d58 d dispaud_div_clks
ffff800081ec2e70 d dispaud_mux_clks
ffff800081ec2fc0 d mout_dispaud_mi2s_p
ffff800081ec2fd0 d mout_dispaud_decon_vclk_p
ffff800081ec2fe0 d mout_dispaud_decon_eclk_p
ffff800081ec2ff0 d mout_dispaud_decon_vclk_user_p
ffff800081ec3000 d mout_dispaud_decon_eclk_user_p
ffff800081ec3010 d mout_dispaud_bus_user_p
ffff800081ec3020 d dispaud_pll_clks
ffff800081ec3090 d dispaud_fixed_clks
ffff800081ec31a8 d dispaud_clk_regs
ffff800081ec3308 d mif_cmu_info
ffff800081ec33a8 d mif_gate_clks
ffff800081ec40c8 d mif_div_clks
ffff800081ec4720 d mif_mux_clks
ffff800081ec4cd0 d mout_mif_busd_p
ffff800081ec4ce8 d mout_mif_cmu_peri_uart0_p
ffff800081ec4cf8 d mout_mif_cmu_peri_uart2_p
ffff800081ec4d08 d mout_mif_cmu_peri_uart1_p
ffff800081ec4d18 d mout_mif_cmu_peri_spi3_p
ffff800081ec4d28 d mout_mif_cmu_peri_spi4_p
ffff800081ec4d38 d mout_mif_cmu_peri_spi1_p
ffff800081ec4d48 d mout_mif_cmu_peri_spi2_p
ffff800081ec4d58 d mout_mif_cmu_peri_spi0_p
ffff800081ec4d68 d mout_mif_cmu_peri_bus_p
ffff800081ec4d78 d mout_mif_cmu_mfcmscl_mscl_p
ffff800081ec4d90 d mout_mif_cmu_mfcmscl_mfc_p
ffff800081ec4da8 d mout_mif_cmu_isp_vra_p
ffff800081ec4dc0 d mout_mif_cmu_isp_sensor2_p
ffff800081ec4dd0 d mout_mif_cmu_isp_sensor1_p
ffff800081ec4de0 d mout_mif_cmu_isp_sensor0_p
ffff800081ec4df0 d mout_mif_cmu_isp_isp_p
ffff800081ec4e00 d mout_mif_cmu_isp_cam_p
ffff800081ec4e10 d mout_mif_cmu_fsys_usb20drd_refclk_p
ffff800081ec4e20 d mout_mif_cmu_fsys_mmc2_p
ffff800081ec4e30 d mout_mif_cmu_fsys_mmc1_p
ffff800081ec4e40 d mout_mif_cmu_fsys_mmc0_p
ffff800081ec4e50 d mout_mif_cmu_fsys_bus_p
ffff800081ec4e60 d mout_mif_cmu_dispaud_decon_vclk_p
ffff800081ec4e70 d mout_mif_cmu_dispaud_decon_eclk_p
ffff800081ec4e80 d mout_mif_cmu_dispaud_bus_p
ffff800081ec4e90 d mif_pll_clks
ffff800081ec4f38 d mif_fixed_factor_clks
ffff800081ec4fc8 d mif_clk_regs
ffff800081ec53e0 d peri_cmu_info
ffff800081ec5480 d top_cmu_info
ffff800081ec5520 d fsys_cmu_info
ffff800081ec55c0 d fsys_gate_clks
ffff800081ec5800 d fsys_mux_clks
ffff800081ec5950 d mout_usb_pll_p
ffff800081ec5960 d mout_fsys_usb30drd_user_p
ffff800081ec5970 d mout_fsys_mmc_sdio_user_p
ffff800081ec5980 d mout_fsys_mmc_embd_user_p
ffff800081ec5990 d mout_fsys_mmc_card_user_p
ffff800081ec59a0 d mout_fsys_bus_user_p
ffff800081ec59b0 d fsys_pll_clks
ffff800081ec59e8 d pll_usb_rate_table
ffff800081ec5a10 d fsys_clk_regs
ffff800081ec5aa8 d core_cmu_info
ffff800081ec5b48 d core_gate_clks
ffff800081ec5cf8 d core_div_clks
ffff800081ec5d30 d core_mux_clks
ffff800081ec5e10 d mout_core_gic_p
ffff800081ec5e20 d mout_core_g3d_user_p
ffff800081ec5e30 d mout_core_cci_user_p
ffff800081ec5e40 d mout_core_bus_user_p
ffff800081ec5e50 d core_clk_regs
ffff800081ec5ec0 d peri_gate_clks
ffff800081ec6520 d peri_mux_clks
ffff800081ec6718 d mout_peri_usi2_user_p
ffff800081ec6728 d mout_peri_usi1_user_p
ffff800081ec6738 d mout_peri_usi0_user_p
ffff800081ec6748 d mout_peri_uart2_user_p
ffff800081ec6758 d mout_peri_uart1_user_p
ffff800081ec6768 d mout_peri_uart0_user_p
ffff800081ec6778 d mout_peri_spi1_user_p
ffff800081ec6788 d mout_peri_spi0_user_p
ffff800081ec6798 d mout_peri_bus_user_p
ffff800081ec67a8 d peri_clk_regs
ffff800081ec6900 d top_gate_clks
ffff800081ec6c30 d top_div_clks
ffff800081ec7170 d top_mux_clks
ffff800081ec7598 d mout_fsys_usb30drd_p
ffff800081ec75a8 d mout_fsys_mmc_sdio_p
ffff800081ec75b8 d mout_fsys_mmc_embd_p
ffff800081ec75c8 d mout_fsys_mmc_card_p
ffff800081ec75d8 d mout_fsys_bus_p
ffff800081ec75e8 d mout_peri_usi2_p
ffff800081ec75f8 d mout_peri_usi1_p
ffff800081ec7608 d mout_peri_usi0_p
ffff800081ec7618 d mout_peri_uart2_p
ffff800081ec7628 d mout_peri_uart1_p
ffff800081ec7638 d mout_peri_uart0_p
ffff800081ec7648 d mout_peri_spi1_p
ffff800081ec7658 d mout_peri_spi0_p
ffff800081ec7668 d mout_peri_bus_p
ffff800081ec7678 d mout_core_g3d_p
ffff800081ec7698 d mout_core_cci_p
ffff800081ec76b8 d mout_core_bus_p
ffff800081ec76d8 d mout_shared1_pll_p
ffff800081ec76e8 d mout_shared0_pll_p
ffff800081ec76f8 d top_pll_clks
ffff800081ec7768 d top_clk_regs
ffff800081ec7958 d peri_cmu_info
ffff800081ec79f8 d cpucl1_cmu_info
ffff800081ec7a98 d cpucl0_cmu_info
ffff800081ec7b38 d top_cmu_info
ffff800081ec7bd8 d dpu_cmu_info
ffff800081ec7c78 d dpu_gate_clks
ffff800081ec7df8 d dpu_div_clks
ffff800081ec7e30 d dpu_mux_clks
ffff800081ec7e68 d mout_dpu_user_p
ffff800081ec7e78 d dpu_clk_regs
ffff800081ec7ec8 d core_cmu_info
ffff800081ec7f68 d core_gate_clks
ffff800081ec8148 d core_div_clks
ffff800081ec8180 d core_mux_clks
ffff800081ec8298 d mout_core_gic_p
ffff800081ec82a8 d mout_core_sss_user_p
ffff800081ec82b8 d mout_core_mmc_embd_user_p
ffff800081ec82c8 d mout_core_cci_user_p
ffff800081ec82d8 d mout_core_bus_user_p
ffff800081ec82e8 d core_clk_regs
ffff800081ec8368 d peri_gate_clks
ffff800081ec8878 d peri_div_clks
ffff800081ec8958 d peri_mux_clks
ffff800081ec8a38 d mout_peri_spi_user_p
ffff800081ec8a48 d mout_peri_hsi2c_user_p
ffff800081ec8a58 d mout_peri_uart_user_p
ffff800081ec8a68 d mout_peri_bus_user_p
ffff800081ec8a78 d peri_clk_regs
ffff800081ec8b90 d mfcmscl_cmu_info
ffff800081ec8c30 d mfcmscl_gate_clks
ffff800081ec8e10 d mfcmscl_div_clks
ffff800081ec8e48 d mfcmscl_mux_clks
ffff800081ec8f28 d mout_mfcmscl_jpeg_user_p
ffff800081ec8f38 d mout_mfcmscl_mcsc_user_p
ffff800081ec8f48 d mout_mfcmscl_m2m_user_p
ffff800081ec8f58 d mout_mfcmscl_mfc_user_p
ffff800081ec8f68 d mfcmscl_clk_regs
ffff800081ec8fe0 d is_cmu_info
ffff800081ec9080 d is_gate_clks
ffff800081ec93e0 d is_div_clks
ffff800081ec9418 d is_mux_clks
ffff800081ec94f8 d mout_is_gdc_user_p
ffff800081ec9508 d mout_is_vra_user_p
ffff800081ec9518 d mout_is_itp_user_p
ffff800081ec9528 d mout_is_bus_user_p
ffff800081ec9538 d is_clk_regs
ffff800081ec95f0 d hsi_cmu_info
ffff800081ec9690 d hsi_gate_clks
ffff800081ec98d0 d hsi_mux_clks
ffff800081ec99b0 d mout_hsi_rtc_p
ffff800081ec99c0 d mout_hsi_usb20drd_user_p
ffff800081ec99d0 d mout_hsi_mmc_card_user_p
ffff800081ec99e0 d mout_hsi_bus_user_p
ffff800081ec99f0 d hsi_clk_regs
ffff800081ec9a70 d g3d_cmu_info
ffff800081ec9b10 d g3d_gate_clks
ffff800081ec9c60 d g3d_div_clks
ffff800081ec9c98 d g3d_mux_clks
ffff800081ec9d40 d g3d_pll_clks
ffff800081ec9d78 d mout_g3d_busd_p
ffff800081ec9d88 d mout_g3d_switch_user_p
ffff800081ec9d98 d mout_g3d_pll_p
ffff800081ec9da8 d g3d_clk_regs
ffff800081ec9e10 d cpucl1_cpu_clks
ffff800081ec9e40 d cpucl1_gate_clks
ffff800081ec9f60 d cpucl1_div_clks
ffff800081eca0e8 d cpucl1_mux_clks
ffff800081eca1c8 d cpucl1_pll_clks
ffff800081eca200 d mout_cpucl1_pll_p
ffff800081eca210 d mout_cpucl1_dbg_user_p
ffff800081eca220 d mout_cpucl1_switch_user_p
ffff800081eca230 d mout_pll_cpucl1_p
ffff800081eca240 d cpucl1_clk_regs
ffff800081eca2e0 d cpucl0_cpu_clks
ffff800081eca310 d exynos850_cluster_clk_d
ffff800081eca4f0 d cpucl0_gate_clks
ffff800081eca610 d cpucl0_div_clks
ffff800081eca798 d cpucl0_mux_clks
ffff800081eca878 d cpucl0_pll_clks
ffff800081eca8b0 d cpu_pll_rates
ffff800081ecab60 d mout_cpucl0_pll_p
ffff800081ecab70 d mout_cpucl0_dbg_user_p
ffff800081ecab80 d mout_cpucl0_switch_user_p
ffff800081ecab90 d mout_pll_cpucl0_p
ffff800081ecaba0 d cpucl0_clk_regs
ffff800081ecac40 d cmgp_cmu_info
ffff800081ecace0 d cmgp_gate_clks
ffff800081ecae60 d cmgp_div_clks
ffff800081ecaf08 d cmgp_mux_clks
ffff800081ecafb0 d cmgp_fixed_clks
ffff800081ecafd8 d mout_cmgp_adc_p
ffff800081ecafe8 d mout_cmgp_usi1_p
ffff800081ecaff8 d mout_cmgp_usi0_p
ffff800081ecb008 d cmgp_clk_regs
ffff800081ecb078 d aud_cmu_info
ffff800081ecb118 d aud_gate_clks
ffff800081ecb538 d aud_div_clks
ffff800081ecb8f0 d aud_mux_clks
ffff800081ecbbc8 d aud_fixed_clks
ffff800081ecbd08 d aud_pll_clks
ffff800081ecbd40 d mout_aud_fm_p
ffff800081ecbd50 d mout_aud_tick_usb_user_p
ffff800081ecbd60 d mout_aud_uaif6_p
ffff800081ecbd70 d mout_aud_uaif5_p
ffff800081ecbd80 d mout_aud_uaif4_p
ffff800081ecbd90 d mout_aud_uaif3_p
ffff800081ecbda0 d mout_aud_uaif2_p
ffff800081ecbdb0 d mout_aud_uaif1_p
ffff800081ecbdc0 d mout_aud_uaif0_p
ffff800081ecbdd0 d mout_aud_cpu_hch_p
ffff800081ecbde0 d mout_aud_cpu_p
ffff800081ecbdf0 d mout_aud_cpu_user_p
ffff800081ecbe00 d mout_aud_pll_p
ffff800081ecbe10 d aud_clk_regs
ffff800081ecbfc0 d apm_cmu_info
ffff800081ecc060 d apm_gate_clks
ffff800081ecc240 d apm_div_clks
ffff800081ecc2e8 d apm_mux_clks
ffff800081ecc470 d apm_fixed_clks
ffff800081ecc510 d mout_apm_i3c_p
ffff800081ecc520 d mout_apm_bus_p
ffff800081ecc540 d mout_clkcmu_chub_bus_p
ffff800081ecc550 d mout_dll_user_p
ffff800081ecc560 d mout_rco_apm_user_p
ffff800081ecc570 d mout_rco_apm_i3c_user_p
ffff800081ecc580 d mout_apm_bus_user_p
ffff800081ecc590 d apm_clk_regs
ffff800081ecc630 d top_gate_clks
ffff800081eccb10 d top_div_clks
ffff800081ecd210 d top_mux_clks
ffff800081ecd868 d mout_dpu_p
ffff800081ecd888 d mout_peri_ip_p
ffff800081ecd8a8 d mout_peri_uart_p
ffff800081ecd8c8 d mout_peri_bus_p
ffff800081ecd8d8 d mout_mfcmscl_jpeg_p
ffff800081ecd8f8 d mout_mfcmscl_mcsc_p
ffff800081ecd918 d mout_mfcmscl_m2m_p
ffff800081ecd938 d mout_mfcmscl_mfc_p
ffff800081ecd958 d mout_is_gdc_p
ffff800081ecd978 d mout_is_vra_p
ffff800081ecd998 d mout_is_itp_p
ffff800081ecd9b8 d mout_is_bus_p
ffff800081ecd9d8 d mout_hsi_usb20drd_p
ffff800081ecd9f8 d mout_hsi_mmc_card_p
ffff800081ecda38 d mout_hsi_bus_p
ffff800081ecda48 d mout_g3d_switch_p
ffff800081ecda68 d mout_cpucl1_dbg_p
ffff800081ecda78 d mout_cpucl1_switch_p
ffff800081ecda98 d mout_cpucl0_dbg_p
ffff800081ecdaa8 d mout_cpucl0_switch_p
ffff800081ecdac8 d mout_core_sss_p
ffff800081ecdae8 d mout_core_mmc_embd_p
ffff800081ecdb28 d mout_core_cci_p
ffff800081ecdb48 d mout_core_bus_p
ffff800081ecdb68 d mout_aud_p
ffff800081ecdb88 d mout_clkcmu_apm_bus_p
ffff800081ecdb98 d mout_mmc_pll_p
ffff800081ecdba8 d mout_shared1_pll_p
ffff800081ecdbb8 d mout_shared0_pll_p
ffff800081ecdbc8 d top_pll_clks
ffff800081ecdc70 d top_clk_regs
ffff800081ecdf58 d peris_cmu_info
ffff800081ecdff8 d top_cmu_info
ffff800081ece098 d peric1_cmu_info
ffff800081ece138 d peric1_gate_clks
ffff800081ecea68 d peric1_mux_clks
ffff800081ecedb0 d mout_peric1_usi13_user_p
ffff800081ecedc0 d mout_peric1_usi12_user_p
ffff800081ecedd0 d mout_peric1_usi11_user_p
ffff800081ecede0 d mout_peric1_usi10_user_p
ffff800081ecedf0 d mout_peric1_usi09_user_p
ffff800081ecee00 d mout_peric1_usi08_user_p
ffff800081ecee10 d mout_peric1_usi07_user_p
ffff800081ecee20 d mout_peric1_usi06_user_p
ffff800081ecee30 d mout_peric1_usi05_user_p
ffff800081ecee40 d mout_peric1_usi04_user_p
ffff800081ecee50 d mout_peric1_uart_bt_user_p
ffff800081ecee60 d mout_peric1_spi_cam1_user_p
ffff800081ecee70 d mout_peric1_spi_cam0_user_p
ffff800081ecee80 d mout_peric1_speedy2_user_p
ffff800081ecee90 d mout_peric1_bus_user_p
ffff800081eceea0 d peric1_clk_regs
ffff800081ecf118 d peric0_cmu_info
ffff800081ecf1b8 d peric0_gate_clks
ffff800081ecf548 d peric0_mux_clks
ffff800081ecf698 d mout_peric0_usi03_user_p
ffff800081ecf6a8 d mout_peric0_usi02_user_p
ffff800081ecf6b8 d mout_peric0_usi01_user_p
ffff800081ecf6c8 d mout_peric0_usi00_user_p
ffff800081ecf6d8 d mout_peric0_uart_dbg_user_p
ffff800081ecf6e8 d mout_peric0_bus_user_p
ffff800081ecf6f8 d peric0_clk_regs
ffff800081ecf7f0 d fsys1_cmu_info
ffff800081ecf890 d fsys1_gate_clks
ffff800081ed0010 d fsys1_mux_clks
ffff800081ed00f0 d mout_fsys1_ufs_card_user_p
ffff800081ed0100 d mout_fsys1_pcie_user_p
ffff800081ed0110 d mout_fsys1_mmc_card_user_p
ffff800081ed0120 d mout_fsys1_bus_user_p
ffff800081ed0130 d fsys1_clk_regs
ffff800081ed02b0 d fsys0_cmu_info
ffff800081ed0350 d fsys0_gate_clks
ffff800081ed0a10 d fsys0_mux_clks
ffff800081ed0b28 d mout_fsys0_usbdrd30_user_p
ffff800081ed0b38 d mout_fsys0_ufs_embd_user_p
ffff800081ed0b48 d mout_fsys0_mmc_embd_user_p
ffff800081ed0b58 d mout_fsys0_dpgtc_user_p
ffff800081ed0b68 d mout_fsys0_bus_user_p
ffff800081ed0b78 d fsys0_clk_regs
ffff800081ed0ce8 d peris_gate_clks
ffff800081ed1348 d peris_mux_clks
ffff800081ed13b8 d mout_peris_gic_p
ffff800081ed13c8 d mout_peris_bus_user_p
ffff800081ed13d8 d peris_clk_regs
ffff800081ed1500 d top_gate_clks
ffff800081ed21c0 d top_fixed_factor_clks
ffff800081ed23a0 d top_div_clks
ffff800081ed31d8 d top_mux_clks
ffff800081ed4160 d mout_cmu_vpu_bus_p
ffff800081ed4180 d mout_cmu_srdz_imgd_p
ffff800081ed41a0 d mout_cmu_srdz_bus_p
ffff800081ed41c0 d mout_cmu_peris_bus_p
ffff800081ed41d0 d mout_cmu_peric1_usi13_p
ffff800081ed41f0 d mout_cmu_peric1_usi12_p
ffff800081ed4210 d mout_cmu_peric1_usi11_p
ffff800081ed4230 d mout_cmu_peric1_usi10_p
ffff800081ed4250 d mout_cmu_peric1_usi09_p
ffff800081ed4270 d mout_cmu_peric1_usi08_p
ffff800081ed4290 d mout_cmu_peric1_usi07_p
ffff800081ed42b0 d mout_cmu_peric1_usi06_p
ffff800081ed42d0 d mout_cmu_peric1_usi05_p
ffff800081ed42f0 d mout_cmu_peric1_usi04_p
ffff800081ed4310 d mout_cmu_peric1_uart_bt_p
ffff800081ed4330 d mout_cmu_peric1_spi_cam1_p
ffff800081ed4350 d mout_cmu_peric1_spi_cam0_p
ffff800081ed4370 d mout_cmu_peric1_speedy2_p
ffff800081ed4390 d mout_cmu_peric1_bus_p
ffff800081ed43a0 d mout_cmu_peric0_usi03_p
ffff800081ed43c0 d mout_cmu_peric0_usi02_p
ffff800081ed43e0 d mout_cmu_peric0_usi01_p
ffff800081ed4400 d mout_cmu_peric0_usi00_p
ffff800081ed4420 d mout_cmu_peric0_uart_dbg_p
ffff800081ed4440 d mout_cmu_peric0_bus_p
ffff800081ed4450 d mout_cmu_mif_switch_p
ffff800081ed4490 d mout_cmu_mfc_bus_p
ffff800081ed44b0 d mout_cmu_iva_bus_p
ffff800081ed44d0 d mout_cmu_isplp_bus_p
ffff800081ed44f0 d mout_cmu_isphq_bus_p
ffff800081ed4510 d mout_cmu_imem_bus_p
ffff800081ed4530 d mout_cmu_hpm_p
ffff800081ed4550 d mout_cmu_g2d_jpeg_p
ffff800081ed4570 d mout_cmu_g2d_g2d_p
ffff800081ed4590 d mout_cmu_fsys1_ufs_card_p
ffff800081ed45b0 d mout_cmu_fsys1_pcie_p
ffff800081ed45c0 d mout_cmu_fsys1_mmc_card_p
ffff800081ed4600 d mout_cmu_fsys1_bus_p
ffff800081ed4610 d mout_fsys0_usbdrd30_p
ffff800081ed4630 d mout_fsys0_ufs_embd_p
ffff800081ed4650 d mout_fsys0_mmc_embd_p
ffff800081ed4690 d mout_fsys0_dpgtc_p
ffff800081ed46b0 d mout_fsys0_bus_p
ffff800081ed46d0 d mout_cmu_dsp_bus_p
ffff800081ed46f0 d mout_cmu_droopdetector_p
ffff800081ed4710 d mout_cmu_dpu_bus_p
ffff800081ed4750 d mout_cmu_dcam_imgd_p
ffff800081ed4770 d mout_cmu_dcam_bus_p
ffff800081ed4790 d mout_cmu_dbg_bus_p
ffff800081ed47b0 d mout_cmu_cpucl1_switch_p
ffff800081ed47d0 d mout_cmu_cpucl0_switch_p
ffff800081ed47f0 d mout_core_bus_p
ffff800081ed4830 d mout_cmu_cis_clk3_p
ffff800081ed4840 d mout_cmu_cis_clk2_p
ffff800081ed4850 d mout_cmu_cis_clk1_p
ffff800081ed4860 d mout_cmu_cis_clk0_p
ffff800081ed4870 d mout_cmu_cam_vra_p
ffff800081ed4890 d mout_cmu_cam_tpu1_p
ffff800081ed48b0 d mout_cmu_cam_tpu0_p
ffff800081ed48d0 d mout_cmu_cam_bus_p
ffff800081ed48f0 d mout_cmu_busc_busphsi2c_p
ffff800081ed4910 d mout_cmu_busc_bus_p
ffff800081ed4950 d mout_cmu_bus1_bus_p
ffff800081ed4970 d mout_cmu_apm_bus_p
ffff800081ed4980 d mout_cmu_abox_cpuabox_p
ffff800081ed49a0 d mout_cp2ap_mif_clk_user_p
ffff800081ed49a8 d mout_pll_shared4_p
ffff800081ed49b8 d mout_pll_shared3_p
ffff800081ed49c8 d mout_pll_shared2_p
ffff800081ed49d8 d mout_pll_shared1_p
ffff800081ed49e8 d mout_pll_shared0_p
ffff800081ed49f8 d top_pll_clks
ffff800081ed4b10 d pll_shared4_rate_table
ffff800081ed4b38 d pll_shared3_rate_table
ffff800081ed4b60 d pll_shared2_rate_table
ffff800081ed4b88 d pll_shared1_rate_table
ffff800081ed4bb0 d pll_shared0_rate_table
ffff800081ed4bd8 d top_clk_regs
ffff800081ed52d0 d peris_cmu_info
ffff800081ed5370 d top_cmu_info
ffff800081ed5410 d peris_gate_clks
ffff800081ed5740 d peris_mux_clks
ffff800081ed57b0 d mout_peris_clk_peris_gic_p
ffff800081ed57c0 d mout_peris_bus_user_p
ffff800081ed57d0 d peris_clk_regs
ffff800081ed58d8 d peric1_cmu_info
ffff800081ed5978 d peric1_gate_clks
ffff800081ed6608 d peric1_div_clks
ffff800081ed68a8 d peric1_mux_clks
ffff800081ed6b80 d mout_peric1_nonbususer_p
ffff800081ed6b90 d mout_peric1_bus_user_p
ffff800081ed6ba0 d peric1_clk_regs
ffff800081ed6ee8 d peric0_cmu_info
ffff800081ed6f88 d peric0_gate_clks
ffff800081ed7a38 d peric0_div_clks
ffff800081ed7ca0 d peric0_mux_clks
ffff800081ed7f40 d mout_peric0_nonbususer_p
ffff800081ed7f50 d mout_peric0_bus_user_p
ffff800081ed7f60 d peric0_clk_regs
ffff800081ed8240 d hsi0_cmu_info
ffff800081ed82e0 d hsi0_gate_clks
ffff800081ed8670 d hsi0_mux_clks
ffff800081ed8750 d mout_hsi0_dpgtc_user_p
ffff800081ed8760 d mout_hsi0_usbdp_debug_user_p
ffff800081ed8770 d mout_hsi0_usb31drd_user_p
ffff800081ed8780 d mout_hsi0_bus_user_p
ffff800081ed8790 d hsi0_clk_regs
ffff800081ed8848 d top_gate_clks
ffff800081ed92c8 d cmu_top_ffactor
ffff800081ed9388 d top_div_clks
ffff800081eda1f8 d top_mux_clks
ffff800081edb0d8 d mout_cmu_clk_cmuref_p
ffff800081edb0f8 d mout_cmu_cmuref_p
ffff800081edb108 d mout_cmu_vra_bus_p
ffff800081edb128 d mout_cmu_tnr_bus_p
ffff800081edb168 d mout_cmu_ssp_bus_p
ffff800081edb188 d mout_cmu_peris_bus_p
ffff800081edb198 d mout_cmu_peric1_ip_p
ffff800081edb1a8 d mout_cmu_peric1_bus_p
ffff800081edb1b8 d mout_cmu_peric0_ip_p
ffff800081edb1c8 d mout_cmu_peric0_bus_p
ffff800081edb1d8 d mout_cmu_npu_bus_p
ffff800081edb218 d mout_cmu_mif_switch_p
ffff800081edb258 d mout_cmu_mif_busp_p
ffff800081edb278 d mout_cmu_mfc0_wfd_p
ffff800081edb298 d mout_cmu_mfc0_mfc0_p
ffff800081edb2b8 d mout_cmu_cmu_boost_cpu_p
ffff800081edb2d8 d mout_cmu_mcsc_gdc_p
ffff800081edb318 d mout_cmu_mcsc_bus_p
ffff800081edb358 d mout_cmu_itp_bus_p
ffff800081edb398 d mout_cmu_ipp_bus_p
ffff800081edb3d8 d mout_cmu_hsi2_pcie_p
ffff800081edb3e8 d mout_cmu_hsi2_bus_p
ffff800081edb3f8 d mout_cmu_hsi1_ufs_embd_p
ffff800081edb418 d mout_cmu_hsi1_ufs_card_p
ffff800081edb438 d mout_cmu_hsi1_pcie_p
ffff800081edb448 d mout_cmu_hsi1_mmc_card_p
ffff800081edb468 d mout_cmu_hsi1_bus_p
ffff800081edb4a8 d mout_cmu_hsi0_usbdp_debug_p
ffff800081edb4b8 d mout_cmu_hsi0_usb31drd_p
ffff800081edb4d8 d mout_cmu_hsi0_dpgtc_p
ffff800081edb4f8 d mout_cmu_hsi0_bus_p
ffff800081edb508 d mout_cmu_hpm_p
ffff800081edb528 d mout_cmu_g2d_mscl_p
ffff800081edb548 d mout_cmu_g2d_g2d_p
ffff800081edb568 d mout_cmu_dsp_bus_p
ffff800081edb5a8 d mout_cmu_dpu_alt_p
ffff800081edb5c8 d mout_cmu_dpu_p
ffff800081edb5d8 d mout_cmu_dns_bus_p
ffff800081edb618 d mout_cmu_dnc_busm_p
ffff800081edb638 d mout_cmu_dnc_bus_p
ffff800081edb658 d mout_cmu_csis_ois_mcu_p
ffff800081edb668 d mout_cmu_csis_bus_p
ffff800081edb688 d mout_cmu_cpucl2_switch_p
ffff800081edb6a8 d mout_cmu_cpucl2_busp_p
ffff800081edb6b8 d mout_cmu_cpucl1_switch_p
ffff800081edb6d8 d mout_cmu_cpucl0_switch_p
ffff800081edb6f8 d mout_cmu_cpucl0_dbg_bus_p
ffff800081edb718 d mout_cmu_core_bus_p
ffff800081edb758 d mout_cmu_cmu_boost_p
ffff800081edb778 d mout_cmu_cis_clk5_p
ffff800081edb788 d mout_cmu_cis_clk4_p
ffff800081edb798 d mout_cmu_cis_clk3_p
ffff800081edb7a8 d mout_cmu_cis_clk2_p
ffff800081edb7b8 d mout_cmu_cis_clk1_p
ffff800081edb7c8 d mout_cmu_cis_clk0_p
ffff800081edb7d8 d mout_cmu_bus1_sss_p
ffff800081edb7f8 d mout_cmu_bus1_bus_p
ffff800081edb818 d mout_cmu_bus0_bus_p
ffff800081edb838 d mout_cmu_aud_cpu_p
ffff800081edb858 d mout_cmu_apm_bus_p
ffff800081edb868 d mout_cmu_dpu_bus_p
ffff800081edb878 d mout_pll_g3d_p
ffff800081edb888 d mout_pll_mmc_p
ffff800081edb898 d mout_pll_shared4_p
ffff800081edb8a8 d mout_pll_shared3_p
ffff800081edb8b8 d mout_pll_shared2_p
ffff800081edb8c8 d mout_pll_shared1_p
ffff800081edb8d8 d mout_pll_shared0_p
ffff800081edb8e8 d top_pll_clks
ffff800081edba70 d top_clk_regs
ffff800081edc100 d top_cmu_info
ffff800081edc1a0 d peris_cmu_info
ffff800081edc240 d peris_gate_clks
ffff800081edc2d0 d peris_mux_clks
ffff800081edc308 d mout_peris_bus_user_p
ffff800081edc318 d peris_clk_regs
ffff800081edc338 d peric1_cmu_info
ffff800081edc3d8 d peric1_gate_clks
ffff800081edc858 d peric1_div_clks
ffff800081edc9e0 d peric1_mux_clks
ffff800081edcbd8 d mout_peric1_usi_p
ffff800081edcbe8 d mout_peric1_ip_user_p
ffff800081edcbf8 d mout_peric1_bus_user_p
ffff800081edcc08 d peric1_clk_regs
ffff800081edcd48 d peric0_cmu_info
ffff800081edcde8 d peric0_gate_clks
ffff800081edd268 d peric0_div_clks
ffff800081edd3f0 d peric0_mux_clks
ffff800081edd5e8 d mout_peric0_usi_p
ffff800081edd5f8 d mout_peric0_ip_user_p
ffff800081edd608 d mout_peric0_bus_user_p
ffff800081edd618 d peric0_clk_regs
ffff800081edd758 d fsys2_cmu_info
ffff800081edd7f8 d fsys2_gate_clks
ffff800081edd8b8 d fsys2_mux_clks
ffff800081edd960 d mout_fsys2_ethernet_user_p
ffff800081edd970 d mout_fsys2_ufs_embd_user_p
ffff800081edd980 d mout_fsys2_bus_user_p
ffff800081edd990 d fsys2_clk_regs
ffff800081edd9c8 d fsys1_cmu_info
ffff800081edda68 d fsys1_gate_clks
ffff800081eddc78 d fsys1_div_clks
ffff800081eddcb0 d fsys1_mux_clks
ffff800081edddc8 d mout_fsys1_mmc_card_p
ffff800081edddd8 d mout_fsys1_usbdrd_user_p
ffff800081eddde8 d mout_fsys1_mmc_card_user_p
ffff800081edddf8 d mout_fsys1_mmc_pll_p
ffff800081edde08 d mout_fsys1_bus_user_p
ffff800081edde18 d fsys1_pll_clks
ffff800081edde50 d fsys1_clk_regs
ffff800081edde58 d fsys0_cmu_info
ffff800081eddef8 d fsys0_gate_clks
ffff800081ede4c8 d fsys0_mux_clks
ffff800081ede538 d mout_fsys0_pcie_user_p
ffff800081ede548 d mout_fsys0_bus_user_p
ffff800081ede558 d fsys0_clk_regs
ffff800081ede678 d dpum_cmu_info
ffff800081ede718 d dpum_gate_clks
ffff800081ede868 d dpum_div_clks
ffff800081ede8a0 d dpum_mux_clks
ffff800081ede8d8 d mout_dpum_bus_user_p
ffff800081ede8e8 d dpum_clk_regs
ffff800081ede930 d core_cmu_info
ffff800081ede9d0 d core_gate_clks
ffff800081edea60 d core_div_clks
ffff800081edea98 d core_mux_clks
ffff800081edead0 d mout_core_bus_user_p
ffff800081edeae0 d core_clk_regs
ffff800081edeb10 d busmc_cmu_info
ffff800081edebb0 d busmc_gate_clks
ffff800081edec10 d busmc_div_clks
ffff800081edec48 d busmc_mux_clks
ffff800081edec80 d mout_busmc_bus_user_p
ffff800081edec90 d busmc_clk_regs
ffff800081edecb0 d top_gate_clks
ffff800081edf580 d top_fixed_factor_clks
ffff800081edf5b0 d top_div_clks
ffff800081ee0030 d top_mux_clks
ffff800081ee0a78 d mout_clkcmu_peric0_bus_p
ffff800081ee0a88 d mout_clkcmu_npu_bus_p
ffff800081ee0ac8 d mout_clkcmu_mif_switch_p
ffff800081ee0b08 d mout_clkcmu_g3d1_switch_p
ffff800081ee0b28 d mout_clkcmu_g3d0_switch_p
ffff800081ee0b48 d mout_clkcmu_g2d_g2d_p
ffff800081ee0b88 d mout_clkcmu_fsys2_ethernet_p
ffff800081ee0bb8 d mout_clkcmu_fsys1_mmc_card_p
ffff800081ee0bd8 d mout_clkcmu_fsys1_usbdrd_p
ffff800081ee0bf8 d mout_clkcmu_fsys1_bus_p
ffff800081ee0c18 d mout_clkcmu_fsys0_pcie_p
ffff800081ee0c28 d mout_clkcmu_fsys0_bus_p
ffff800081ee0c48 d mout_clkcmu_dpum_bus_p
ffff800081ee0c78 d mout_clkcmu_dptx_dpgtc_p
ffff800081ee0c98 d mout_clkcmu_dptx_bus_p
ffff800081ee0cb8 d mout_clkcmu_cpucl0_cluster_p
ffff800081ee0cf8 d mout_clkcmu_cpucl0_switch_p
ffff800081ee0d18 d mout_clkcmu_core_bus_p
ffff800081ee0d58 d mout_clkcmu_busc_bus_p
ffff800081ee0d78 d mout_clkcmu_aud_bus_p
ffff800081ee0d98 d mout_clkcmu_aud_cpu_p
ffff800081ee0dd0 d mout_clkcmu_apm_bus_p
ffff800081ee0df0 d mout_clkcmu_acc_bus_p
ffff800081ee0e10 d mout_clkcmu_cmu_cmuref_p
ffff800081ee0e20 d mout_clkcmu_cmu_boost_p
ffff800081ee0e40 d mout_shared4_pll_p
ffff800081ee0e50 d mout_shared3_pll_p
ffff800081ee0e60 d mout_shared2_pll_p
ffff800081ee0e70 d mout_shared1_pll_p
ffff800081ee0e80 d mout_shared0_pll_p
ffff800081ee0e90 d top_pll_clks
ffff800081ee0fa8 d top_clk_regs
ffff800081ee1470 d cpucl2_cmu_info
ffff800081ee1510 d cpucl1_cmu_info
ffff800081ee15b0 d cpucl0_cmu_info
ffff800081ee1650 d top_cmu_info
ffff800081ee16f0 d hsi2_cmu_info
ffff800081ee1790 d hsi2_div_clks
ffff800081ee1800 d hsi2_mux_clks
ffff800081ee18e0 d mout_clkcmu_hsi2_ethernet_user_p
ffff800081ee18f0 d mout_hsi2_ethernet_p
ffff800081ee1900 d mout_clkcmu_hsi2_ufs_embd_user_p
ffff800081ee1910 d mout_clkcmu_hsi2_noc_ufs_user_p
ffff800081ee1920 d hsi2_pll_clks
ffff800081ee1958 d hsi2_clk_regs
ffff800081ee1998 d hsi1_cmu_info
ffff800081ee1a38 d hsi1_mux_clks
ffff800081ee1b18 d mout_hsi1_usbdrd_p
ffff800081ee1b28 d mout_hsi1_usbdrd_user_p
ffff800081ee1b38 d mout_hsi1_noc_user_p
ffff800081ee1b48 d mout_hsi1_mmc_card_user_p
ffff800081ee1b58 d hsi1_clk_regs
ffff800081ee1b78 d hsi0_cmu_info
ffff800081ee1c18 d hsi0_div_clks
ffff800081ee1c50 d hsi0_mux_clks
ffff800081ee1c88 d mout_hsi0_noc_user_p
ffff800081ee1c98 d hsi0_clk_regs
ffff800081ee1ca8 d misc_cmu_info
ffff800081ee1d48 d misc_fixed_factor_clks
ffff800081ee1da8 d misc_div_clks
ffff800081ee1de0 d misc_mux_clks
ffff800081ee1e50 d mout_misc_gic_p
ffff800081ee1e60 d mout_misc_noc_user_p
ffff800081ee1e70 d misc_clk_regs
ffff800081ee1e98 d peric1_cmu_info
ffff800081ee1f38 d peric1_div_clks
ffff800081ee21a0 d peric1_mux_clks
ffff800081ee2478 d mout_peric1_usi_p
ffff800081ee2488 d mout_peric1_noc_user_p
ffff800081ee2498 d mout_peric1_ip_user_p
ffff800081ee24a8 d peric1_clk_regs
ffff800081ee2568 d peric0_cmu_info
ffff800081ee2608 d peric0_div_clks
ffff800081ee2870 d peric0_mux_clks
ffff800081ee2b48 d mout_peric0_usi_p
ffff800081ee2b58 d mout_peric0_noc_user_p
ffff800081ee2b68 d mout_peric0_ip_user_p
ffff800081ee2b78 d peric0_clk_regs
ffff800081ee2c38 d cpucl2_div_clks
ffff800081ee2d88 d cpucl2_mux_clks
ffff800081ee2ea0 d cpucl2_pll_clks
ffff800081ee2ed8 d mout_cpucl2_core_p
ffff800081ee2ef0 d mout_cpucl2_cluster_p
ffff800081ee2f08 d mout_cpucl2_switch_user_p
ffff800081ee2f18 d mout_cpucl2_cluster_user_p
ffff800081ee2f28 d mout_pll_cpucl2_p
ffff800081ee2f38 d cpucl2_clk_regs
ffff800081ee2fa8 d cpucl1_div_clks
ffff800081ee30f8 d cpucl1_mux_clks
ffff800081ee3210 d cpucl1_pll_clks
ffff800081ee3248 d mout_cpucl1_core_p
ffff800081ee3260 d mout_cpucl1_cluster_p
ffff800081ee3278 d mout_cpucl1_switch_user_p
ffff800081ee3288 d mout_cpucl1_cluster_user_p
ffff800081ee3298 d mout_pll_cpucl1_p
ffff800081ee32a8 d cpucl1_clk_regs
ffff800081ee3318 d cpucl0_div_clks
ffff800081ee34d8 d cpucl0_mux_clks
ffff800081ee3628 d cpucl0_pll_clks
ffff800081ee3660 d cpu_pll_rates
ffff800081ee37f0 d mout_cpucl0_core_p
ffff800081ee3808 d mout_cpucl0_cluster_p
ffff800081ee3820 d mout_cpucl0_switch_user_p
ffff800081ee3830 d mout_cpucl0_dbg_user_p
ffff800081ee3840 d mout_cpucl0_cluster_user_p
ffff800081ee3850 d mout_pll_cpucl0_p
ffff800081ee3860 d cpucl0_clk_regs
ffff800081ee38e8 d top_fixed_factor_clks
ffff800081ee3d98 d top_div_clks
ffff800081ee4930 d top_mux_clks
ffff800081ee56c0 d mout_clkcmu_taa_noc_p
ffff800081ee5700 d mout_clkcmu_ssp_noc_p
ffff800081ee5720 d mout_clkcmu_snw_noc_p
ffff800081ee5760 d mout_clkcmu_sdma_noc_p
ffff800081ee57a0 d mout_clkcmu_peric1_ip_p
ffff800081ee57b0 d mout_clkcmu_peric1_noc_p
ffff800081ee57c0 d mout_clkcmu_peric0_ip_p
ffff800081ee57d0 d mout_clkcmu_peric0_noc_p
ffff800081ee57e0 d mout_clkcmu_nocl2_noc_p
ffff800081ee5820 d mout_clkcmu_nocl1_noc_p
ffff800081ee5860 d mout_clkcmu_nocl0_noc_p
ffff800081ee58a0 d mout_clkcmu_misc_noc_p
ffff800081ee58c0 d mout_clkcmu_mif_nocp_p
ffff800081ee58e0 d mout_clkcmu_mif_switch_p
ffff800081ee5920 d mout_clkcmu_mfd_noc_p
ffff800081ee5960 d mout_clkcmu_mfc_wfd_p
ffff800081ee5980 d mout_clkcmu_mfc_mfc_p
ffff800081ee59a0 d mout_clkcmu_m2m_jpeg_p
ffff800081ee59c0 d mout_clkcmu_m2m_noc_p
ffff800081ee59e0 d mout_clkcmu_isp_noc_p
ffff800081ee5a20 d mout_clkcmu_hsi2_ethernet_p
ffff800081ee5a40 d mout_clkcmu_hsi2_ufs_embd_p
ffff800081ee5a60 d mout_clkcmu_hsi2_noc_ufs_p
ffff800081ee5a80 d mout_clkcmu_hsi2_noc_p
ffff800081ee5aa0 d mout_clkcmu_hsi1_mmc_card_p
ffff800081ee5ac0 d mout_clkcmu_hsi1_usbdrd_p
ffff800081ee5ae0 d mout_clkcmu_hsi1_noc_p
ffff800081ee5b00 d mout_clkcmu_hsi0_noc_p
ffff800081ee5b20 d mout_clkcmu_gnpu_noc_p
ffff800081ee5b60 d mout_clkcmu_g3d_nocp_p
ffff800081ee5b80 d mout_clkcmu_g3d_switch_p
ffff800081ee5ba0 d mout_clkcmu_dsp_noc_p
ffff800081ee5be0 d mout_clkcmu_dpuf_noc_p
ffff800081ee5c18 d mout_clkcmu_dpub_dsim_p
ffff800081ee5c28 d mout_clkcmu_dpub_noc_p
ffff800081ee5c60 d mout_clkcmu_dptx_dposc_p
ffff800081ee5c70 d mout_clkcmu_dptx_dpgtc_p
ffff800081ee5c90 d mout_clkcmu_dptx_noc_p
ffff800081ee5cb0 d mout_clkcmu_dnc_noc_p
ffff800081ee5cf0 d mout_clkcmu_cpucl2_cluster_p
ffff800081ee5d30 d mout_clkcmu_cpucl2_switch_p
ffff800081ee5d50 d mout_clkcmu_cpucl1_cluster_p
ffff800081ee5d90 d mout_clkcmu_cpucl1_switch_p
ffff800081ee5db0 d mout_clkcmu_cpucl0_dbg_p
ffff800081ee5dd0 d mout_clkcmu_cpucl0_cluster_p
ffff800081ee5e10 d mout_clkcmu_cpucl0_switch_p
ffff800081ee5e30 d mout_clkcmu_aud_noc_p
ffff800081ee5e50 d mout_clkcmu_aud_cpu_p
ffff800081ee5e90 d mout_clkcmu_apm_noc_p
ffff800081ee5eb0 d mout_clkcmu_acc_orb_p
ffff800081ee5ef0 d mout_clkcmu_acc_noc_p
ffff800081ee5f30 d mout_clkcmu_cmu_cmuref_p
ffff800081ee5f40 d mout_clkcmu_cmu_boost_p
ffff800081ee5f60 d mout_mmc_pll_p
ffff800081ee5f70 d mout_shared5_pll_p
ffff800081ee5f80 d mout_shared4_pll_p
ffff800081ee5f90 d mout_shared3_pll_p
ffff800081ee5fa0 d mout_shared2_pll_p
ffff800081ee5fb0 d mout_shared1_pll_p
ffff800081ee5fc0 d mout_shared0_pll_p
ffff800081ee5fd0 d top_pll_clks
ffff800081ee6158 d top_clk_regs
ffff800081ee65d8 d misc_cmu_info
ffff800081ee6678 d top_cmu_info
ffff800081ee6718 d peric1_cmu_info
ffff800081ee67b8 d peric1_gate_clks
ffff800081ee6d58 d peric1_div_clks
ffff800081ee6ee0 d peric1_mux_clks
ffff800081ee70a0 d mout_peric1_nonbususer_p
ffff800081ee70b0 d mout_peric1_bus_user_p
ffff800081ee70c0 d peric1_clk_regs
ffff800081ee7308 d peric0_cmu_info
ffff800081ee73a8 d peric0_gate_clks
ffff800081ee7df8 d peric0_div_clks
ffff800081ee8060 d peric0_mux_clks
ffff800081ee8300 d mout_peric0_usi_usi_user_p
ffff800081ee8310 d mout_peric0_usi0_uart_user_p
ffff800081ee8320 d mout_peric0_i3c_user_p
ffff800081ee8330 d mout_peric0_bus_user_p
ffff800081ee8340 d peric0_clk_regs
ffff800081ee8738 d misc_gate_clks
ffff800081ee9398 d misc_div_clks
ffff800081ee9408 d misc_mux_clks
ffff800081ee94b0 d mout_misc_gic_p
ffff800081ee94c0 d mout_misc_sss_user_p
ffff800081ee94d0 d mout_misc_bus_user_p
ffff800081ee94e0 d misc_clk_regs
ffff800081ee98d0 d hsi2_cmu_info
ffff800081ee9970 d hsi2_gate_clks
ffff800081eea3f0 d hsi2_mux_clks
ffff800081eea4d0 d mout_hsi2_ufs_embd_user_p
ffff800081eea4e0 d mout_hsi2_pcie_user_p
ffff800081eea4f0 d mout_hsi2_mmc_card_user_p
ffff800081eea500 d mout_hsi2_bus_user_p
ffff800081eea510 d cmu_hsi2_clk_regs
ffff800081eea850 d hsi0_cmu_info
ffff800081eea8f0 d hsi0_fixed_clks
ffff800081eea968 d hsi0_gate_clks
ffff800081eeb0b8 d hsi0_div_clks
ffff800081eeb0f0 d hsi0_mux_clks
ffff800081eeb358 d cmu_hsi0_pll_clks
ffff800081eeb390 d cmu_hsi0_usb_pll_rates
ffff800081eeb3d8 d mout_hsi0_usb31drd_p
ffff800081eeb3f8 d mout_hsi0_usb20_ref_p
ffff800081eeb408 d mout_hsi0_bus_p
ffff800081eeb418 d mout_hsi0_usbdpdbg_user_p
ffff800081eeb428 d mout_hsi0_usb31drd_user_p
ffff800081eeb438 d mout_hsi0_usb20_user_p
ffff800081eeb448 d mout_hsi0_tcxo_user_p
ffff800081eeb458 d mout_hsi0_dpgtc_user_p
ffff800081eeb468 d mout_hsi0_bus_user_p
ffff800081eeb478 d mout_hsi0_alt_user_p
ffff800081eeb488 d mout_pll_usb_p
ffff800081eeb498 d hsi0_clk_regs
ffff800081eeb7a0 d apm_cmu_info
ffff800081eeb840 d apm_gate_clks
ffff800081eec3e0 d apm_div_clks
ffff800081eec4c0 d apm_mux_clks
ffff800081eec530 d apm_fixed_clks
ffff800081eec5a8 d mout_apm_funcsrc_p
ffff800081eec5c0 d mout_apm_func_p
ffff800081eec5e0 d apm_clk_regs
ffff800081eec810 d cmu_top_gate_clks
ffff800081eed590 d cmu_top_ffactor
ffff800081eed5f0 d cmu_top_div_clks
ffff800081eee578 d cmu_top_mux_clks
ffff800081eef538 d mout_cmu_cmuref_p
ffff800081eef548 d mout_cmu_tpu_uart_p
ffff800081eef568 d mout_cmu_tpu_tpuctl_p
ffff800081eef5a8 d mout_cmu_tpu_tpu_p
ffff800081eef5e8 d mout_cmu_tpu_bus_p
ffff800081eef628 d mout_cmu_top_cmuref_p
ffff800081eef648 d mout_cmu_top_boost_option1_p
ffff800081eef658 d mout_cmu_tnr_bus_p
ffff800081eef698 d mout_cmu_peric1_ip_p
ffff800081eef6b8 d mout_cmu_peric1_bus_p
ffff800081eef6d8 d mout_cmu_peric0_ip_p
ffff800081eef6f8 d mout_cmu_peric0_bus_p
ffff800081eef718 d mout_cmu_pdp_vra_p
ffff800081eef758 d mout_cmu_pdp_bus_p
ffff800081eef798 d mout_cmu_misc_sss_p
ffff800081eef7b8 d mout_cmu_misc_bus_p
ffff800081eef7d8 d mout_cmu_mif_switch_p
ffff800081eef818 d mout_cmu_mif_busp_p
ffff800081eef838 d mout_cmu_mfc_mfc_p
ffff800081eef878 d mout_cmu_mcsc_mcsc_p
ffff800081eef8b8 d mout_cmu_mcsc_itsc_p
ffff800081eef8f8 d mout_cmu_itp_bus_p
ffff800081eef938 d mout_cmu_ipp_bus_p
ffff800081eef978 d mout_cmu_hsi2_ufs_embd_p
ffff800081eef998 d mout_cmu_hsi2_pcie0_p
ffff800081eef9a8 d mout_cmu_hsi2_mmc_card_p
ffff800081eef9c8 d mout_cmu_hsi2_bus_p
ffff800081eefa08 d mout_cmu_hsi1_pcie_p
ffff800081eefa18 d mout_cmu_hsi1_bus_p
ffff800081eefa40 d mout_cmu_hsi0_usbdpdbg_p
ffff800081eefa50 d mout_cmu_hsi0_usb31drd_p
ffff800081eefa60 d mout_cmu_hsi0_dpgtc_p
ffff800081eefa80 d mout_cmu_hsi0_bus_p
ffff800081eefac0 d mout_cmu_hpm_p
ffff800081eefae0 d mout_cmu_gdc_scsc_p
ffff800081eefb20 d mout_cmu_gdc_gdc1_p
ffff800081eefb60 d mout_cmu_gdc_gdc0_p
ffff800081eefba0 d mout_cmu_g3d_switch_p
ffff800081eefbe0 d mout_cmu_g3d_glb_p
ffff800081eefc20 d mout_cmu_g3d_busd_p
ffff800081eefc60 d mout_cmu_g3aa_g3aa_p
ffff800081eefca0 d mout_cmu_g2d_mscl_p
ffff800081eefce0 d mout_cmu_g2d_g2d_p
ffff800081eefd20 d mout_cmu_eh_bus_p
ffff800081eefd60 d mout_cmu_dpu_p
ffff800081eefda0 d mout_cmu_dns_bus_p
ffff800081eefde0 d mout_cmu_disp_bus_p
ffff800081eefe20 d mout_cmu_csis_bus_p
ffff800081eefe60 d mout_cmu_cpucl2_switch_p
ffff800081eefea0 d mout_cmu_cpucl1_switch_p
ffff800081eefee0 d mout_cmu_cpucl0_switch_p
ffff800081eeff20 d mout_cmu_cpucl0_dbg_p
ffff800081eeff60 d mout_cmu_core_bus_p
ffff800081eeffa0 d mout_cmu_cmu_boost_option1_p
ffff800081eeffb0 d mout_cmu_cmu_boost_p
ffff800081eeffd0 d mout_cmu_cis_clk0_7_p
ffff800081ef0010 d mout_cmu_bus2_bus_p
ffff800081ef0050 d mout_cmu_bus1_bus_p
ffff800081ef0090 d mout_cmu_bus0_bus_p
ffff800081ef00d0 d mout_cmu_bo_bus_p
ffff800081ef0110 d mout_pll_spare_p
ffff800081ef0120 d mout_pll_shared3_p
ffff800081ef0130 d mout_pll_shared2_p
ffff800081ef0140 d mout_pll_shared1_p
ffff800081ef0150 d mout_pll_shared0_p
ffff800081ef0160 d cmu_top_pll_clks
ffff800081ef0278 d cmu_top_clk_regs
ffff800081ef0bb8 d pmc_match
ffff800081ef0d48 d pmc_match
ffff800081ef0ed8 d rockchip_grf_dt_match
ffff800081ef1838 d rk3588_sysgrf
ffff800081ef1848 d rk3588_defaults
ffff800081ef1858 d rk3576_iocgrf
ffff800081ef1868 d rk3576_defaults_ioc_grf
ffff800081ef1878 d rk3576_sysgrf
ffff800081ef1888 d rk3576_defaults_sys_grf
ffff800081ef18a8 d rk3566_pipegrf
ffff800081ef18b8 d rk3566_defaults
ffff800081ef18e8 d rk3399_grf
ffff800081ef18f8 d rk3399_defaults
ffff800081ef1908 d rk3368_grf
ffff800081ef1918 d rk3368_defaults
ffff800081ef1928 d rk3328_grf
ffff800081ef1938 d rk3328_defaults
ffff800081ef1948 d rk3288_grf
ffff800081ef1958 d rk3288_defaults
ffff800081ef1978 d rk3228_grf
ffff800081ef1988 d rk3228_defaults
ffff800081ef1998 d rk3128_grf
ffff800081ef19a8 d rk3128_defaults
ffff800081ef19c8 d rk3036_grf
ffff800081ef19d8 d rk3036_defaults
ffff800081ef19e8 d sunxi_mbus_platforms
ffff800081ef1a70 d car_match
ffff800081ef1fe8 d apbmisc_match
ffff800081ef2498 d gpu_process_speedos
ffff800081ef24a8 d cpu_process_speedos
ffff800081ef24b8 d soc_process_speedos
ffff800081ef24c8 d __setup_str_pd_ignore_unused_setup
ffff800081ef24d9 d __setup_str_regulator_ignore_unused_setup
ffff800081ef24f8 d sunxi_early_reset_dt_ids
ffff800081ef2688 d __setup_str_sysrq_always_enabled_setup
ffff800081ef269d d __setup_str_param_setup_earlycon_console_alias
ffff800081ef26a5 d __setup_str_param_setup_earlycon
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ffff80008212c0e0 d mt7981_wa_aice3_pins
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ffff80008212c650 d mt7986_wf_5g_pins
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ffff80008212c760 d mt7986_emmc_51_pins
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ffff80008212c848 d mt7986_uart1_3_rx_tx_pins
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ffff800082184d80 D acpi_rs_convert_pin_group
ffff800082184da8 D acpi_rs_convert_pin_config
ffff800082184de0 D acpi_rs_convert_uart_serial_bus
ffff800082184e40 D acpi_rs_convert_spi_serial_bus
ffff800082184e98 D acpi_rs_convert_i2c_serial_bus
ffff800082184ee0 D acpi_rs_convert_csi2_serial_bus
ffff800082184f18 D acpi_rs_convert_pin_function
ffff800082184f50 D acpi_rs_convert_clock_input
ffff800082184f70 D acpi_rs_convert_gpio
ffff800082184fb8 d acpi_gbl_previous_thread_id
ffff800082184fc0 D acpi_gbl_region_types
ffff800082185020 D acpi_gbl_highest_dstate_names
ffff800082185040 D acpi_gbl_lowest_dstate_names
ffff800082185068 D acpi_gbl_sleep_state_names
ffff800082185098 D acpi_gbl_db_output_flags
ffff800082185099 D acpi_gbl_early_initialization
ffff80008218509a D acpi_gbl_shutdown
ffff80008218509c D acpi_gbl_fadt_index
ffff8000821850a0 D acpi_gbl_xfacs_index
ffff8000821850a4 D acpi_gbl_facs_index
ffff8000821850a8 D acpi_gbl_dsdt_index
ffff8000821850ac D acpi_dbg_level
ffff8000821850b0 D acpi_gbl_trace_dbg_layer
ffff8000821850b4 D acpi_gbl_trace_dbg_level
ffff8000821850b8 D acpi_gbl_max_loop_iterations
ffff8000821850bc D acpi_gbl_use_global_lock
ffff8000821850bd D acpi_gbl_runtime_namespace_override
ffff8000821850be D acpi_gbl_use32_bit_facs_addresses
ffff8000821850bf D acpi_gbl_enable_table_validation
ffff8000821850c0 D acpi_gbl_use_default_register_widths
ffff8000821850c1 D acpi_gbl_create_osi_method
ffff8000821850c2 D acpi_gbl_auto_serialize_methods
ffff8000821850c8 d acpi_default_supported_interfaces
ffff800082185380 D acpi_gbl_clock_input_scale
ffff800082185398 D acpi_gbl_clock_input_mode
ffff8000821853a8 D acpi_gbl_ptyp_decode
ffff800082185418 D acpi_gbl_pt_decode
ffff800082185458 D acpi_gbl_fc_decode
ffff800082185478 D acpi_gbl_sb_decode
ffff800082185498 D acpi_gbl_bpb_decode
ffff8000821854d8 D acpi_gbl_ed_decode
ffff8000821854e8 D acpi_gbl_dp_decode
ffff8000821854f8 D acpi_gbl_cpo_decode
ffff800082185508 D acpi_gbl_cph_decode
ffff800082185518 D acpi_gbl_wm_decode
ffff800082185528 D acpi_gbl_sm_decode
ffff800082185538 D acpi_gbl_am_decode
ffff800082185548 D acpi_gbl_sbt_decode
ffff800082185570 D acpi_gbl_ct_decode
ffff800082185580 D acpi_gbl_dts_decode
ffff8000821855b0 D acpi_gbl_ior_decode
ffff8000821855d0 D acpi_gbl_ppc_decode
ffff8000821855f0 D acpi_gbl_typ_decode
ffff800082185610 D acpi_gbl_ttp_decode
ffff800082185620 D acpi_gbl_trs_decode
ffff800082185630 D acpi_gbl_siz_decode
ffff800082185650 D acpi_gbl_shr_decode
ffff800082185670 D acpi_gbl_rw_decode
ffff800082185680 D acpi_gbl_rng_decode
ffff8000821856a0 D acpi_gbl_phy_decode
ffff8000821856c0 D acpi_gbl_mtp_decode
ffff8000821856e0 D acpi_gbl_min_decode
ffff8000821856f0 D acpi_gbl_mem_decode
ffff800082185710 D acpi_gbl_max_decode
ffff800082185720 D acpi_gbl_ll_decode
ffff800082185740 D acpi_gbl_io_decode
ffff800082185750 D acpi_gbl_he_decode
ffff800082185760 D acpi_gbl_dec_decode
ffff800082185770 D acpi_gbl_consume_decode
ffff800082185780 D acpi_gbl_config_decode
ffff8000821857a0 D acpi_gbl_bm_decode
ffff8000821857b0 d pci_mcfg_list
ffff8000821857c0 d mcfg_quirks
ffff800082189c80 d acpi_ac_driver
ffff800082189d48 d slot_list
ffff800082189d58 d slot_list_lock
ffff800082189d78 d container_handler
ffff800082189e18 d empty_nhlt
ffff800082189e40 d pxm_to_node_map
ffff80008218a640 d node_to_pxm_map
ffff80008218ae40 d memory_device_handler
ffff80008218aee0 d cache_time
ffff80008218aee8 d acpi_battery_driver
ffff80008218b040 d acpi_battery_list
ffff80008218b050 d hook_mutex
ffff80008218b070 d battery_hook_list
ffff80008218b080 d acpi_battery_groups
ffff80008218b090 d acpi_battery_attrs
ffff80008218b0a0 d alarm_attr
ffff80008218b0c0 d acpi_hed_notify_list
ffff80008218b0f0 d acpi_hed_driver
ffff80008218b248 d whea_uuid_str.0
ffff80008218b270 d apei_resources_all
ffff80008218b290 d erst_ins_type
ffff80008218b3c0 d erst_record_id_cache
ffff80008218b3f8 d erst_info
ffff80008218b480 d cxl_cper_prot_err_fifo
ffff80008218bb18 d ghes_devs
ffff80008218bb28 d vendor_record_notify_list
ffff80008218bb58 d _rs.20
ffff80008218bb78 d _rs.18
ffff80008218bb98 d _rs.16
ffff80008218bbb8 d _rs.15
ffff80008218bbd8 d _rs.8
ffff80008218bbf8 d _rs.6
ffff80008218bc18 d ghes_list_mutex
ffff80008218bc38 d ghes_hed
ffff80008218bc48 d ghes_notifier_hed
ffff80008218bc60 d ghes_devs_mutex
ffff80008218bc80 d _rs.4
ffff80008218bca0 d ratelimit_corrected.11
ffff80008218bcc0 d ratelimit_uncorrected.10
ffff80008218bce0 d _rs.14
ffff80008218bd00 d ghes_sea
ffff80008218bd10 d ghes_platform_driver
ffff80008218bdd8 D cxl_cper_fifo
ffff80008218d070 d int340x_thermal_handler
ffff80008218d110 d iort_fwnode_list
ffff80008218d120 d iort_msi_chip_list
ffff80008218d130 d amba_handler
ffff80008218d1d0 d viot_pci_ranges
ffff80008218d1e0 d viot_iommus
ffff80008218d1f0 d viot_mmio_endpoints
ffff80008218d200 D pnp_lock
ffff80008218d220 d pnp_protocols
ffff80008218d230 D pnp_global
ffff80008218d240 d pnp_card_drivers
ffff80008218d250 D pnp_cards
ffff80008218d260 d dev_attr_name
ffff80008218d280 d dev_attr_card_id
ffff80008218d2a0 d pnp_reserve_irq
ffff80008218d2e0 d pnp_reserve_dma
ffff80008218d300 d pnp_reserve_io
ffff80008218d340 d pnp_reserve_mem
ffff80008218d380 D pnp_res_mutex
ffff80008218d3a0 D pnp_dev_groups
ffff80008218d3b0 d pnp_dev_attrs
ffff80008218d3d0 d dev_attr_id
ffff80008218d3f0 d dev_attr_resources
ffff80008218d410 d dev_attr_options
ffff80008218d430 d pnp_fixups
ffff80008218d550 d system_pnp_driver
ffff80008218d620 D pnpacpi_protocol
ffff80008218d9a8 d hp_ccsr_uuid
ffff80008218d9c0 d amba_proxy_drv
ffff80008218da78 d amba_dev_groups
ffff80008218da88 d amba_dev_attrs
ffff80008218daa0 d dev_attr_resource
ffff80008218dac0 d dev_attr_id
ffff80008218dae0 d tegra_ahb_driver
ffff80008218dba8 d clocks_mutex
ffff80008218dbc8 d clocks
ffff80008218dbd8 d prepare_lock
ffff80008218dbf8 d clk_notifier_list
ffff80008218dc08 d clk_rpm_list_lock
ffff80008218dc28 d of_clk_mutex
ffff80008218dc48 d of_clk_providers
ffff80008218dc58 d all_lists
ffff80008218dc70 d orphan_list
ffff80008218dc80 d clk_debug_lock
ffff80008218dca0 d print_fmt_clk_rate_request
ffff80008218dd38 d print_fmt_clk_duty_cycle
ffff80008218dd88 d print_fmt_clk_phase
ffff80008218ddb8 d print_fmt_clk_parent
ffff80008218dde8 d print_fmt_clk_rate_range
ffff80008218de40 d print_fmt_clk_rate
ffff80008218de78 d print_fmt_clk
ffff80008218de90 d trace_event_fields_clk_rate_request
ffff80008218df80 d trace_event_fields_clk_duty_cycle
ffff80008218e020 d trace_event_fields_clk_phase
ffff80008218e098 d trace_event_fields_clk_parent
ffff80008218e110 d trace_event_fields_clk_rate_range
ffff80008218e1b0 d trace_event_fields_clk_rate
ffff80008218e228 d trace_event_fields_clk
ffff80008218e278 d trace_event_type_funcs_clk_rate_request
ffff80008218e298 d trace_event_type_funcs_clk_duty_cycle
ffff80008218e2b8 d trace_event_type_funcs_clk_phase
ffff80008218e2d8 d trace_event_type_funcs_clk_parent
ffff80008218e2f8 d trace_event_type_funcs_clk_rate_range
ffff80008218e318 d trace_event_type_funcs_clk_rate
ffff80008218e338 d trace_event_type_funcs_clk
ffff80008218e358 d event_clk_rate_request_done
ffff80008218e3d0 d event_clk_rate_request_start
ffff80008218e448 d event_clk_set_duty_cycle_complete
ffff80008218e4c0 d event_clk_set_duty_cycle
ffff80008218e538 d event_clk_set_phase_complete
ffff80008218e5b0 d event_clk_set_phase
ffff80008218e628 d event_clk_set_parent_complete
ffff80008218e6a0 d event_clk_set_parent
ffff80008218e718 d event_clk_set_rate_range
ffff80008218e790 d event_clk_set_max_rate
ffff80008218e808 d event_clk_set_min_rate
ffff80008218e880 d event_clk_set_rate_complete
ffff80008218e8f8 d event_clk_set_rate
ffff80008218e970 d event_clk_unprepare_complete
ffff80008218e9e8 d event_clk_unprepare
ffff80008218ea60 d event_clk_prepare_complete
ffff80008218ead8 d event_clk_prepare
ffff80008218eb50 d event_clk_disable_complete
ffff80008218ebc8 d event_clk_disable
ffff80008218ec40 d event_clk_enable_complete
ffff80008218ecb8 d event_clk_enable
ffff80008218ed30 D __SCK__tp_func_clk_rate_request_done
ffff80008218ed38 D __SCK__tp_func_clk_rate_request_start
ffff80008218ed40 D __SCK__tp_func_clk_set_duty_cycle_complete
ffff80008218ed48 D __SCK__tp_func_clk_set_duty_cycle
ffff80008218ed50 D __SCK__tp_func_clk_set_phase_complete
ffff80008218ed58 D __SCK__tp_func_clk_set_phase
ffff80008218ed60 D __SCK__tp_func_clk_set_parent_complete
ffff80008218ed68 D __SCK__tp_func_clk_set_parent
ffff80008218ed70 D __SCK__tp_func_clk_set_rate_range
ffff80008218ed78 D __SCK__tp_func_clk_set_max_rate
ffff80008218ed80 D __SCK__tp_func_clk_set_min_rate
ffff80008218ed88 D __SCK__tp_func_clk_set_rate_complete
ffff80008218ed90 D __SCK__tp_func_clk_set_rate
ffff80008218ed98 D __SCK__tp_func_clk_unprepare_complete
ffff80008218eda0 D __SCK__tp_func_clk_unprepare
ffff80008218eda8 D __SCK__tp_func_clk_prepare_complete
ffff80008218edb0 D __SCK__tp_func_clk_prepare
ffff80008218edb8 D __SCK__tp_func_clk_disable_complete
ffff80008218edc0 D __SCK__tp_func_clk_disable
ffff80008218edc8 D __SCK__tp_func_clk_enable_complete
ffff80008218edd0 D __SCK__tp_func_clk_enable
ffff80008218edd8 d of_fixed_factor_clk_driver
ffff80008218eea0 d of_fixed_clk_driver
ffff80008218ef68 d gpio_clk_driver
ffff80008218f030 d gated_fixed_clk_driver
ffff80008218f0f8 d scmi_clocks_driver
ffff80008218f1a8 d clk_dvp_driver
ffff80008218f270 d bcm2835_clk_driver
ffff80008218f338 d __compound_literal.51
ffff80008218f350 d __compound_literal.50
ffff80008218f388 d __compound_literal.49
ffff80008218f3c0 d __compound_literal.48
ffff80008218f3f8 d __compound_literal.47
ffff80008218f430 d __compound_literal.46
ffff80008218f468 d __compound_literal.45
ffff80008218f4a0 d __compound_literal.44
ffff80008218f4d8 d __compound_literal.43
ffff80008218f510 d __compound_literal.42
ffff80008218f548 d __compound_literal.41
ffff80008218f580 d __compound_literal.40
ffff80008218f5b8 d __compound_literal.39
ffff80008218f5f0 d __compound_literal.38
ffff80008218f628 d __compound_literal.37
ffff80008218f660 d __compound_literal.36
ffff80008218f698 d __compound_literal.35
ffff80008218f6d0 d __compound_literal.34
ffff80008218f708 d __compound_literal.33
ffff80008218f740 d __compound_literal.32
ffff80008218f778 d __compound_literal.31
ffff80008218f7b0 d __compound_literal.30
ffff80008218f7e8 d __compound_literal.29
ffff80008218f820 d __compound_literal.28
ffff80008218f858 d __compound_literal.27
ffff80008218f890 d __compound_literal.26
ffff80008218f8c8 d __compound_literal.25
ffff80008218f900 d __compound_literal.24
ffff80008218f938 d __compound_literal.23
ffff80008218f970 d __compound_literal.22
ffff80008218f9a8 d __compound_literal.21
ffff80008218f9e0 d __compound_literal.20
ffff80008218fa08 d __compound_literal.19
ffff80008218fa30 d __compound_literal.18
ffff80008218fa58 d __compound_literal.17
ffff80008218faa0 d __compound_literal.16
ffff80008218fac8 d __compound_literal.15
ffff80008218faf0 d __compound_literal.14
ffff80008218fb18 d __compound_literal.13
ffff80008218fb40 d __compound_literal.12
ffff80008218fb88 d __compound_literal.11
ffff80008218fbb0 d __compound_literal.10
ffff80008218fbd8 d __compound_literal.9
ffff80008218fc00 d __compound_literal.8
ffff80008218fc28 d __compound_literal.7
ffff80008218fc70 d __compound_literal.6
ffff80008218fc98 d __compound_literal.5
ffff80008218fce0 d __compound_literal.4
ffff80008218fd08 d __compound_literal.3
ffff80008218fd30 d __compound_literal.2
ffff80008218fd58 d __compound_literal.1
ffff80008218fd80 d __compound_literal.0
ffff80008218fdc8 d bcm2835_aux_clk_driver
ffff80008218fe90 d hi3516cv300_crg_driver
ffff80008218ff58 d wdt_mux_table
ffff80008218ff60 d pwm_mux_table
ffff80008218ff70 d mmc2_mux_table
ffff80008218ff78 d fmc_mux_table
ffff80008218ff90 d uart_mux_table
ffff80008218ff98 d hi3559av100_crg_driver
ffff800082190060 d hi3559av100_gate_clks
ffff8000821908b0 d hi3559av100_mux_clks_crg
ffff800082190b38 d hi3559av100_shub_gate_clks
ffff800082190da0 d hi3559av100_shub_div_clks
ffff800082190e20 d hi3559av100_shub_mux_clks
ffff800082190eb0 d hi3559av100_shub_fixed_rate_clks
ffff8000821910b8 d hi3559av100_pll_clks
ffff800082191118 d shub_uart_div_clk_table
ffff800082191130 d shub_spi_clk_table
ffff800082191150 d shub_uart_source_clk_mux_p
ffff800082191170 d shub_uart_source_clk_mux_table
ffff800082191180 d shub_source_clk_mux_p
ffff8000821911a0 d shub_source_clk_mux_table
ffff8000821911b0 d a73_clksel_mux_p
ffff8000821911c8 d uart_mux_p
ffff8000821911e0 d sysbus_mux_p
ffff8000821911f0 d sysapb_mux_p
ffff800082191200 d mmc_mux_p
ffff800082191240 d fmc_mux_p
ffff800082191280 d hi3660_clk_driver
ffff800082191348 d hi3670_clk_driver
ffff800082191410 d hi3798cv200_crg_driver
ffff8000821914d8 d hi3798cv200_phase_clks
ffff800082191568 d hi3798cv200_mux_clks
ffff800082191688 d mmc_phase_degrees
ffff8000821916a8 d mmc_phase_regvals
ffff8000821916c8 d sdio_mux_table
ffff8000821916d8 d comphy_mux_table
ffff8000821916e0 d mmc_mux_table
ffff8000821916f8 d hi3660_stub_clk_driver
ffff8000821917c0 d hi3660_stub_clks
ffff8000821918e0 d __compound_literal.3
ffff800082191918 d __compound_literal.2
ffff800082191950 d __compound_literal.1
ffff800082191988 d __compound_literal.0
ffff8000821919c0 d clk_mt6765_drv
ffff800082191a88 d top_aud_divs
ffff800082191c10 d clk_mt6779_drv
ffff800082191cd8 d clk_mt6779_infra_drv
ffff800082191da0 d clk_mt6795_apmixed_drv
ffff800082191e68 d pllfhs
ffff800082192128 d clk_mt6795_infracfg_drv
ffff8000821921f0 d infra_ao_idx_map
ffff800082192200 d infra_ao_rst_ofs
ffff800082192208 d clk_mt6795_pericfg_drv
ffff8000821922d0 d peri_idx_map
ffff8000821922d8 d clk_mt6795_topckgen_drv
ffff8000821923a0 d top_aud_divs
ffff800082192758 d clk_mt6795_mfg_drv
ffff800082192820 d clk_mt6795_mm_drv
ffff8000821928e8 d clk_mt6795_vdecsys_drv
ffff8000821929b0 d clk_mt6795_vencsys_drv
ffff800082192a78 d clk_mt6797_drv
ffff800082192b40 d clk_mt7981_apmixed_drv
ffff800082192c08 d clk_mt7981_topckgen_drv
ffff800082192cd0 d top_aud_divs
ffff800082192d08 d clk_mt7981_infracfg_drv
ffff800082192dd0 d clk_mt7981_eth_drv
ffff800082192e98 d clk_mt7986_apmixed_drv
ffff800082192f60 d clk_mt7986_topckgen_drv
ffff800082193028 d clk_mt7986_infracfg_drv
ffff8000821930f0 d clk_mt7986_eth_drv
ffff8000821931b8 d clk_mt7988_apmixed_drv
ffff800082193280 d clk_mt7988_topckgen_drv
ffff800082193348 d mcu_muxes
ffff8000821933b8 d clk_mt7988_infracfg_drv
ffff800082193480 d infra_rst_desc
ffff8000821934a8 d infra_idx_map
ffff8000821934b0 d infra_rst_ofs
ffff8000821934b8 d clk_mt7988_eth_drv
ffff800082193580 d ethwarp_idx_map
ffff800082193588 d ethwarp_rst_ofs
ffff800082193590 d clk_mt7988_xfipll_drv
ffff800082193658 d clk_mt8167_apmixed_drv
ffff800082193720 d clk_mt8167_drv
ffff8000821937e8 d clk_mt8167_audsys_drv
ffff8000821938b0 d clk_mt8167_imgsys_drv
ffff800082193978 d clk_mt8167_mfgcfg_drv
ffff800082193a40 d clk_mt8167_mm_drv
ffff800082193b08 d clk_mt8167_vdec_drv
ffff800082193bd0 d clk_mt8183_apmixed_drv
ffff800082193c98 d clk_mt8183_drv
ffff800082193d60 d infra_rst_ofs
ffff800082193d68 d top_aud_comp
ffff800082194008 d mcu_muxes
ffff8000821940b0 d clk_mt8186_apmixed_drv
ffff800082194178 d pllfhs
ffff800082194540 d clk_mt8186_topck_drv
ffff800082194608 d top_muxes
ffff800082194838 d clk_mt8186_infra_ao_drv
ffff800082194900 d infra_ao_rst_desc
ffff800082194928 d infra_ao_idx_map
ffff800082194930 d infra_ao_rst_ofs
ffff800082194940 d clk_mt8186_cam_drv
ffff800082194a08 d clk_mt8186_img_drv
ffff800082194ad0 d clk_mt8186_imp_iic_wrap_drv
ffff800082194b98 d clk_mt8186_ipe_drv
ffff800082194c60 d clk_mt8186_mcu_drv
ffff800082194d28 d mcu_muxes
ffff800082194dd0 d clk_mt8186_mdp_drv
ffff800082194e98 d clk_mt8186_mfg_drv
ffff800082194f60 d clk_mt8186_mm_drv
ffff800082195028 d clk_mt8186_vdec_drv
ffff8000821950f0 d clk_mt8186_venc_drv
ffff8000821951b8 d clk_mt8186_wpe_drv
ffff800082195280 d clk_mt8188_apmixed_drv
ffff800082195348 d clk_mt8188_topck_drv
ffff800082195410 d clk_mt8188_peri_ao_drv
ffff8000821954d8 d clk_mt8188_infra_ao_drv
ffff8000821955a0 d infra_ao_idx_map
ffff8000821955a8 d infra_ao_rst_ofs
ffff8000821955b8 d clk_mt8188_adsp_audio26m_drv
ffff800082195680 d clk_mt8188_cam_drv
ffff800082195748 d cam_sys_rst_ofs
ffff800082195750 d clk_mt8188_ccu_drv
ffff800082195818 d clk_mt8188_imgsys_main_drv
ffff8000821958e0 d img_sys_rst_ofs
ffff8000821958e8 d clk_mt8188_imp_iic_wrap_drv
ffff8000821959b0 d clk_mt8188_ipe_drv
ffff800082195a78 d ipe_sys_rst_ofs
ffff800082195a80 d clk_mt8188_mfgcfg_drv
ffff800082195b48 d clk_mt8188_vdec_drv
ffff800082195c10 d clk_mt8188_vdo0_drv
ffff800082195cd8 d clk_mt8188_vdo1_drv
ffff800082195da0 d clk_mt8188_venc1_drv
ffff800082195e68 d clk_mt8188_vpp0_drv
ffff800082195f30 d clk_mt8188_vpp1_drv
ffff800082195ff8 d clk_mt8188_wpe_drv
ffff8000821960c0 d clk_mt8192_apmixed_drv
ffff800082196188 d pllfhs
ffff800082196398 d clk_mt8192_drv
ffff800082196460 d infra_ao_idx_map
ffff800082196470 d infra_ao_rst_ofs
ffff800082196480 d top_muxes
ffff800082196918 d clk_mt8192_aud_drv
ffff8000821969e0 d clk_mt8192_cam_drv
ffff800082196aa8 d clk_mt8192_img_drv
ffff800082196b70 d clk_mt8192_imp_iic_wrap_drv
ffff800082196c38 d clk_mt8192_ipe_drv
ffff800082196d00 d clk_mt8192_mdp_drv
ffff800082196dc8 d clk_mt8192_mfg_drv
ffff800082196e90 d clk_mt8192_mm_drv
ffff800082196f58 d clk_mt8192_msdc_drv
ffff800082197020 d clk_mt8192_scp_adsp_drv
ffff8000821970e8 d clk_mt8192_vdec_drv
ffff8000821971b0 d clk_mt8192_venc_drv
ffff800082197278 d clk_mt8195_apmixed_drv
ffff800082197340 d pllfhs
ffff8000821976b0 d clk_mt8195_topck_drv
ffff800082197778 d clk_mt8195_peri_ao_drv
ffff800082197840 d clk_mt8195_infra_ao_drv
ffff800082197908 d infra_ao_rst_desc
ffff800082197930 d infra_ao_idx_map
ffff800082197940 d infra_ao_rst_ofs
ffff800082197950 d clk_mt8195_apusys_pll_drv
ffff800082197a18 d clk_mt8195_cam_drv
ffff800082197ae0 d clk_mt8195_ccu_drv
ffff800082197ba8 d clk_mt8195_img_drv
ffff800082197c70 d clk_mt8195_imp_iic_wrap_drv
ffff800082197d38 d clk_mt8195_ipe_drv
ffff800082197e00 d clk_mt8195_mfg_drv
ffff800082197ec8 d clk_mt8195_scp_adsp_drv
ffff800082197f90 d clk_mt8195_vdec_drv
ffff800082198058 d clk_mt8195_vdo0_drv
ffff800082198120 d clk_mt8195_vdo1_drv
ffff8000821981e8 d clk_mt8195_venc_drv
ffff8000821982b0 d clk_mt8195_vpp0_drv
ffff800082198378 d clk_mt8195_vpp1_drv
ffff800082198440 d clk_mt8195_wpe_drv
ffff800082198508 d clk_mt8196_apmixed_drv
ffff8000821985d0 d clk_mt8196_topck_drv
ffff800082198698 d clk_mt8196_topck_drv
ffff800082198760 d clk_mt8196_vlp_drv
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