Ð þíc8\Ü(=\¤SolidRun CN9130 Clearfog BaseD!solidrun,cn9130-clearfog-basesolidrun,cn9130-sr-sommarvell,cn9130aliases ,/soc/bus@f0000000/serial@512000 4/soc/bus@f0000000/serial@5121005*mpp0mpp1mpp2mpp3mpp4mpp5mpp6mpp7mpp8mpp9mpp10mpp127sdio#gpio@1040!marvell,armada-8k-gpioH@OVfr~À‘Ÿclock!marvell,ap807-clockœ#system-controller@6f8000!sysconsimple-mfd¢o€thermal-sensor@80!marvell,armada-ap807-thermal¢€­ ¾©# clock-cpu!marvell,ap807-cpu-clockŸœ#thermal-zonesap-ic-thermal¿Õã tripsap-critó† ÿÐ  criticalcooling-mapsap-cpu0-thermal¿èÕèã tripscpu0-hotóLÿÐ passive# cpu0-emergósÿÐ passive#cooling-mapsmap0-hot   map0-ermerg  ap-cpu1-thermal¿èÕèã tripscpu1-hotóLÿÐ passive#cpu1-emergósÿÐ passive#cooling-mapsmap1-hot  map1-emerg  ap-cpu2-thermal¿èÕèã tripscpu2-hotóLÿÐ passive#cpu2-emergósÿÐ passive#cooling-mapsmap2-hotmap2-emergap-cpu3-thermal¿èÕèã tripscpu3-hotóLÿÐ passive#cpu3-emergósÿÐ passive#cooling-mapsmap3-bhotmap3-emergcp0-ic-thermal¿Õãtripscritó† ÿÐ  criticalcooling-mapscpuscpu@0#cpu!arm,cortex-a72¢/psci=ŸLÀY@kx€…@—¤# cpu@1#cpu!arm,cortex-a72¢/psci=ŸLÀY@kx€…@—¤# cpu@100#cpu!arm,cortex-a72¢/psci=ŸLÀY@kx€…@—¤#cpu@101#cpu!arm,cortex-a72¢/psci=ŸLÀY@kx€…@—¤#l2-cache0!cacheN[@mµÁ#l2-cache1!cacheN[@mµÁ#cp0-bus !simple-bus­›bus@f2000000 !simple-bus›òethernet@0!marvell,armada-7k-pp22¢�°"<Ÿ *Õpp_clkgop_clkmg_clkmg_core_clkaxi_clkÏöokayÉethernet-port@0P¾'+/37;?CG�2éhif0hif1hif2hif3hif4hif5hif6hif7hif8link¢ùöokay in-band-status 10gbase-r#ethernet-port@1P¾(,048<@DH€2éhif0hif1hif2hif3hif4hif5hif6hif7hif8link¢ùöokay' !sgmiiethernet-port@2P¾)-159=AEI2éhif0hif1hif2hif3hif4hif5hif6hif7hif8link¢ùöokayÇdefault½" rgmii-id'#phy@120000!marvell,comphy-cp110¢`Ï$ŸÕmg_clkmg_core_clkaxi_clkphy@0¢+#.phy@1¢+#)phy@2¢+#phy@3¢+#!phy@4¢+#,phy@5¢+#7mdio@12a200!marvell,orion-mdio¢¢0Ÿ öokay½$ethernet-phy@0¢6ð a##ledsled@0¢G?wanMkeepled@1¢G?wanMkeepethernet-phy@1¢ 6ð a? # ledsled@0¢G?lanMkeepled@1¢G?lanMkeepmdio@12a600!marvell,xmdio¢¦$Ÿ ödisabledinterrupt-controller@1e0000!marvell,cp110-icu¢@interrupt-controller@10!marvell,cp110-icu-nsr¢ ý”%#interrupt-controller@50!marvell,cp110-icu-sei¢Pý” #(rtc@284000!marvell,armada-8k-rtc¢(@ (@€$ [rtcrtc-soc¾Msystem-controller@440000!sysconsimple-mfd¢D #clock!marvell,cp110-clockœ#gpio@100!marvell,armada-8k-gpioHO Vfr& ~ð‘ ¾VUTSý ÕcoreaxiŸöokay#3sim-select-hogePn zsim-selectgpio@140!marvell,armada-8k-gpioH@OVfr& ~ð‘ ¾RQPOý ÕcoreaxiŸöokay#:pinctrl!!marvell,cp115-standalone-pinctrl½'„default#&cp0-ge2-rgmii-pinsH*mpp44mpp45mpp46mpp47mpp48mpp49mpp50mpp51mpp52mpp53mpp54mpp557ge1#"cp0-i2c0-pins *mpp37mpp387i2c0#1cp0-mdio-pins *mpp0mpp17ge#$cp0-spi1-pins*mpp13mpp14mpp15mpp167spi1#/cp0-reg-vhv-pins*mpp417gpio#9cp0-i2c1-pins *mpp35mpp367i2c1#4cp0-mmc0-pins**mpp43mpp56mpp57mpp58mpp59mpp60mpp617sdio#6cp0-spi1-cs1-pins*mpp127spi1#0cp0-uart-pins *mpp2mpp37uart1#5cp0-expander0-pins*mpp47gpio#2cp0-rear-button-pins*mpp317gpio#<cp0-sim-select-pins*mpp277gpio#'system-controller@400000!sysconsimple-mfd¢@thermal-sensor@70!marvell,armada-cp110-thermal¢p ‘(t©#utmi@580000!marvell,cp110-utmi-phy¢X Ïöokayusb-phy@0¢+#*usb-phy@1¢+#-usb@500000$!marvell,armada-8k-xhcigeneric-xhci¢P@ɾj ÕcoreregŸöokay )* ¥comphyutmi¯+»hostusb@510000$!marvell,armada-8k-xhcigeneric-xhci¢Q@ɾi ÕcoreregŸöokay ,- ¥comphyutmi»hostsata@540000$!marvell,armada-8k-ahcigeneric-ahci¢TɾkŸöokaysata-port@0¢ ödisabledsata-port@1¢öokay.xor@6a0000%!marvell,armada-7k-xormarvell,xor-v2¢jkÉ” ÕcoreregŸxor@6c0000%!marvell,armada-7k-xormarvell,xor-v2¢lmÉ” ÕcoreregŸspi@700600!marvell,armada-380-spi¢pP ÕcoreaxiŸ ödisabledspi@700680!marvell,armada-380-spi¢p€P ÕcoreaxiŸöokayÇdefault½/0ÃkIÒflash@0!jedec,spi-nor¢Ãúð€i2c@701000!marvell,mv78230-i2c¢p ¾x ÕcoreregŸöokayÇdefault½1Õ† eeprom@53 !atmel,24c02¢Sågpio-expander@20 !nxp,pca9555¢ Vf½2Çdefault­3¾#8pcie2-0-clkreq-hogePîzpcie2.0-clkreqpcie2-0-w-disable-hogePôzpcie2.0-w-disableusb3-ilimit-hogePîzusb3-current-limitm2-devslp-hogeP ô zm.2 devslpm2-full-card-power-off-hogePôzm2-full-card-power-offm2-reset-hogeP ô zm2-resetadc@4c!microchip,mcp3021¢Leeprom@52 !atmel,24c02¢Råi2c@701100!marvell,mv78230-i2c¢p ¾y ÕcoreregŸöokayÕ† ½4Çdefault#;serial@702000!snps,dw-apb-uart¢p ¦¾z°Õbaudclkapb_pclkŸöokay½5Çdefaultserial@702100!snps,dw-apb-uart¢p!¦¾{°Õbaudclkapb_pclkŸ ödisabledserial@702200!snps,dw-apb-uart¢p"¦¾|°Õbaudclkapb_pclkŸ ödisabledserial@702300!snps,dw-apb-uart¢p#¦¾}°Õbaudclkapb_pclkŸ ödisablednand-controller@720000D!marvell,armada-8k-nand-controllermarvell,armada370-nand-controller¢rT¾s ÕcoreregŸÏ ödisabledtrng@7600003!marvell,armada-8k-rnginside-secure,safexcel-eip76¢v}¾_ ÕcoreregŸöokaymmc@780000!marvell,armada-cp110-sdhci¢x¾ ÕcoreaxiŸÉöokay½6Çdefaultýÿcrypto@800000!inside-secure,safexcel-eip197b¢€ 0¾XYZ[\W éring0ring1ring2ring3eipmem ÕcoreregŸÉpcie@f2600000#!marvell,armada8k-pciesnps,dw-pcie ¢ò`ßð [ctrlconfigý#pciÉ”ÿ›‚ÀÀð%¾3 ÕcoreregŸ  ödisabledpcie@f2620000#!marvell,armada8k-pciesnps,dw-pcie ¢òbàð [ctrlconfigý#pciÉ”ÿ›‚ààð%¾3 ÕcoreregŸ  ödisabledpcie@f2640000#!marvell,armada8k-pciesnps,dw-pcie ¢òdáð [ctrlconfigý#pciÉ”ÿ›‚ááð%¾3 ÕcoreregŸ öokay7 =8chosenIserial0:115200n8regulator-1-8!regulator-fixedU1v8dw@|w@#regulator-vhv-1-8!regulator-fixedUvhv-1v8dw@|w@½9Çdefault P: ”regulator-usb3-vbus0!regulator-fixedUvbus0dLK@|LK@ P8#+sfp!sff,sfp§; ¯8  ¹8 È8 Ù8 èÐ#gpio-keys !gpio-keys½<Çdefaultbutton-0 Rear Button P3rfkill-m2-gnss !rfkill-gpio m.2 GNSS#gps .8 rfkill-m2-wwan !rfkill-gpio m.2 WWAN#wwan .8 #address-cells#size-cellsmodelcompatibleserial0serial1gpio0spi0gpio1gpio2spi1spi2ethernet0ethernet1ethernet2i2c0mmc0rtc0i2c1mmc1methodrangesregno-mapinterrupt-parentinterruptsdma-coherent#iommu-cells#global-interruptsstatus#interrupt-cellsinterrupt-controllerphandlemsi-controllerarm,msi-base-spiarm,msi-num-spismarvell,odmi-framesmarvell,spi-basemarvell,spi-rangesmsi-parentclocksreg-shiftreg-io-widthpinctrl-0pinctrl-namesclock-namesmarvell,xenon-phy-slow-modebus-widthvqmmc-supplyno-sdionon-removablemarvell,pinsmarvell,functionoffsetngpiosgpio-controller#gpio-cellsgpio-rangesmarvell,pwm-offset#pwm-cells#clock-cells#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistypetripcooling-devicedevice_typeenable-method#cooling-cellsi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecache-levelcache-unifiedmarvell,system-controllerinterrupt-namesport-idgop-port-idmanagedphysphy-modesfpphy#phy-cellsmarvell,reg-initcolordefault-statereg-namesgpio-hogoutput-highline-namepintrl-namesinterrupts-extendedphy-namesvbus-supplydr_modespi-max-frequencyclock-frequencypagesizeinputoutput-lowno-1-8-vbus-rangeinterrupt-map-maskinterrupt-mapnum-lanesreset-gpiosstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highi2c-buslos-gpiosmod-def0-gpiostx-disable-gpiostx-fault-gpiosmaximum-power-milliwattlabellinux,can-disablelinux,coderadio-typeshutdown-gpios