Ð þíÅ8x( M@$mediatek,mt8188-evbmediatek,mt8188 +!7MediaTek MT8188 evaluation boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dsc@1c009000T/soc/ethdr@1c114000[/soc/mailbox@10320000`/soc/mailbox@10330000e/soc/merge0@1c014000l/soc/merge@1c10c000s/soc/merge@1c10d000z/soc/merge@1c10e000�/soc/merge@1c10f000ˆ/soc/merge@1c110000�/soc/mutex@1c016000–/soc/mutex@1c101000�/soc/padding@1c11d000¦/soc/padding@1c11e000¯/soc/padding@1c11f000¸/soc/padding@1c120000Á/soc/padding@1c121000Ê/soc/padding@1c122000Ó/soc/padding@1c123000Ü/soc/padding@1c124000å/soc/rdma@1c104000ð/soc/rdma@1c105000û/soc/rdma@1c106000/soc/rdma@1c107000/soc/rdma@1c108000/soc/rdma@1c109000'/soc/rdma@1c10a0002/soc/rdma@1c10b000=/soc/serial@11001100E/soc/i2c@11280000J/soc/i2c@11e00000O/soc/i2c@11281000T/soc/i2c@11282000Y/soc/i2c@11e01000^/soc/i2c@11ec0000c/soc/i2c@11ec1000h/soc/mmc@11230000cpus+cpu@0mcpuarm,cortex-a55y}psci‹w5”›®¾€Ë@Ý€ê€÷@ €';J cpu@100mcpuarm,cortex-a55y}psci‹w5”›®¾€Ë@Ý€ê€÷@ €';J cpu@200mcpuarm,cortex-a55y}psci‹w5”›®¾€Ë@Ý€ê€÷@ €';J cpu@300mcpuarm,cortex-a55y}psci‹w5”›®¾€Ë@Ý€ê€÷@ €';J cpu@400mcpuarm,cortex-a55y}psci‹w5”›®¾€Ë@Ý€ê€÷@ €';J cpu@500mcpuarm,cortex-a55y}psci‹w5”›®¾€Ë@Ý€ê€÷@ €';Jcpu@600mcpuarm,cortex-a78y}psci‹šøÚ›®¾Ë@Ýê÷@ ';Jcpu@700mcpuarm,cortex-a78y}psci‹šøÚ›®¾Ë@Ýê÷@ ';Jcpu-mapcluster0core0R core1R core2R core3R core4R core5Rcore6Rcore7Ridle-statesVpscicpu-off-larm,idle-statecz‹2œ_¬DJcpu-off-barm,idle-statecz‹-œŒ¬äJcluster-off-larm,idle-statecz‹7œ›¬HJcluster-off-barm,idle-statecz‹2œÈ¬èJl2-cache0cache½ÀÍ@ßÉJl2-cache1cache½ÀÍ@ßÉJl3-cachecache½À Í@ßÉJoscillator-13m fixed-clock׋Æ]@äclk13mJ3oscillator-26m fixed-clock׋Œº€äclk26mJ5oscillator-32k fixed-clock׋€äclk32kopp-table-gpuoperating-points-v2÷J[opp-390000000>í€ Æÿopp-431000000°‰À öìÿopp-4730000001h@ 'Àÿopp-515000000²FÀ X”ÿopp-556000000!#ã ‰hÿopp-598000000#¤Á€ º<ÿopp-640000000&%  ëÿopp-670000000'ïc€ äÿopp-700000000)¹' L¸ÿopp-730000000+‚ê€ }Œÿopp-760000000-L® ®`ÿopp-790000000/q€ ß4ÿopp-8350000001ÅÀ (rÿopp-8800000004s¼ q°ÿopp-9150000006‰ÊÀ ÓX�opp-915000000-56‰ÊÀ ¢„0opp-915000000-66‰ÊÀ q°popp-9500000008ŸÙ€ 5�opp-950000000-58ŸÙ€ ÓX0opp-950000000-68ŸÙ€ q°ppmu-a55arm,cortex-a55-pmu (pmu-a78arm,cortex-a78-pmu (psci arm,psci-1.0„smcsound3 Edisabledthermal-zonescpu-little0-thermalLèZ–ptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0—Hœ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little1-thermalLèZ–ptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0—Hœ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little2-thermalLèZ–ptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0—Hœ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little3-thermalLèZ–ptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0—Hœ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-big0-thermalLèZdptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0—œÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-big1-thermalLèZdptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0—œÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿapu-thermalLèZúptripstrip-alert0€LŒÐtpassivetrip-alert1€sŒÐthottrip-crit€† Œ tcriticalgpu-thermalLèZúptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0— œÿÿÿÿÿÿÿÿgpu1-thermalLèZúptripstrip-alert0€LŒÐtpassiveJtrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcooling-mapsmap0— œÿÿÿÿÿÿÿÿadsp-thermalLèZúptripstrip-alert0€LŒÐtpassivetrip-alert1€sŒÐthottrip-crit€† Œ tcriticalvdo-thermalLèZúptripstrip-alert0€LŒÐtpassivetrip-alert1€sŒÐthottrip-crit€† Œ tcriticalinfra-thermalLèZúptripstrip-alert0€LŒÐtpassivetrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcam1-thermalLèZúptripstrip-alert0€LŒÐtpassivetrip-alert1€sŒÐthottrip-crit€† Œ tcriticalcam2-thermalLèZúptripstrip-alert0€LŒÐtpassivetrip-alert1€sŒÐthottrip-crit€† Œ tcriticaltimerarm,armv8-timer @(   ‹Æ]@soc+ simple-bus«¯performance-controller@11bc10mediatek,cpufreq-hw y¼ ½0 ¶Jinterrupt-controller@c000000 arm,gic-v3Ðá ø y   ( Jppi-partitionsinterrupt-partition-0 Jinterrupt-partition-1 Jsyscon@10000000 mediatek,mt8188-topckgensyscony×J"syscon@10001000#mediatek,mt8188-infracfg-aosyscony×J#syscon@10003000mediatek,mt8188-pericfgsyscony0×JApinctrl@10005000mediatek,mt8188-pinctrl`yPÀáâê°0#iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint-=I °ø(ëÐJ adsp-uart-pinspins-tx-rxU#$i2c0-pinsJJpins-busU87\Ëi2c1-pinsJTpins-busU:9\Ëi2c2-pinsJKpins-busU<;\Ëi2c3-pinsJLpins-busU>=\Ëi2c4-pinsJUpins-busU@?\Ëi2c5-pinsJWpins-busUBA\Ëi2c6-pinsJXpins-busUDC\Ëmmc0-default-pinsJGpins-cmd-dat$U¡ Ÿžš™˜—œiv\epins-clkU�v…fpins-rstU›v\emmc0-uhs-pinsJHpins-cmd-dat$U¡ Ÿžš™˜—œiv\epins-clk-dsU�¢v…fpins-rstU›v\enor-pinsJRpins-io-ck U}€…pins-io-cs U~�‚\spi0-pinsJ;pins-spiUEFGH”spi1-pinsJ=pins-spiUKLMN”spi2-pinsJ>pins-spiUOPQR”uart0-pinsJ:pins-rx-txU \syscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfdy`power-controller!mediatek,mt8188-power-controller+¡J6power-domain@0y+¡power-domain@1yµ!"¼mfgaltÈ#+¡power-domain@2y¡power-domain@3y¡power-domain@4y¡power-domain@15yàµ"""" "3"4"="¹"¾$ $ $$$$$$$$$$$$$$$$$ û¼topcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1È#+¡power-domain@16yHµ"»"À%%%%%%%A¼cfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-busÈ#+¡power-domain@20y0µ"º"¿&&&&8¼cfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6È#¡power-domain@22yµ'¼ss-vdec1-soc-l1È#+¡power-domain@23yµ( ¼ss-vdec2-l1È#¡power-domain@29y µ""" "½¼camccubuscfgckÈ#+¡power-domain@30y(µ)))))6¼ss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsysÈ#+¡power-domain@32y µ)*+$¼ss-camb-subss-camb-rawss-camb-yuv¡power-domain@31yµ),-$¼ss-cama-subss-cama-rawss-cama-yuv¡power-domain@17y(µ"¼"Á...&¼cfgckcfgxoss-larb2ss-larb3ss-galsÈ#+¡power-domain@9y µ"@"? ¼bushdcpÈ#¡power-domain@18yÈ#¡power-domain@19yÈ#¡power-domain@24y µ////0¼ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sramÈ#¡power-domain@21yµ00¼ss-wpe-l7ss-wpe-l7pceÈ#¡power-domain@5yÈ#µ1 ¼ss-pextp-fmem¡power-domain@7yµ"0"1¼seninf0seninf1¡power-domain@6y¡power-domain@10y µ"E"D ¼busmainÈ#+¡power-domain@11y È#+¡power-domain@14yµ"F¼asmÈ#¡power-domain@13y µ"S"2¼a1sysintbusadspckÈ#¡power-domain@12y È#¡power-domain@8yµ1  ¼ethermacÈ#¡watchdog@10007000mediatek,mt8188-wdtypÚJ7syscon@1000c000"mediatek,mt8188-apmixedsyssysconyÀ×J!timer@10017000,mediatek,mt8188-timermediatek,mt6765-timeryp( µ3pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsyscony@#pwrap(óµ## ¼spiwrappmicmediatek,mt6359øÐò  Þadcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1)vs18 5P!‘Àh„buck_vgpu11)vgpu118€P7˜ˆhÈ ­„buck_vmodem)vmodem8€PÈà˜*hÈbuck_vpu)vpu8€P7˜ˆhÈ ­„buck_vcore)vcore8€PÖ ˜ˆhÈ ­„buck_vs2)vs28 5Pjh„buck_vpa)vpa8¡ P7±Ðh,buck_vproc2)vproc28€P7˜LhÈ ­buck_vproc1)vproc18€P7˜LhÈ ­buck_vcore_sshub )vcore_sshub8€P7buck_vgpu11_sshub )vgpu11_sshub8€P7ldo_vaud18)vaud188w@Pw@hðldo_vsim1)vsim18ð P/M`ldo_vibr)vibr8O€P2Z ldo_vrf12)vrf128ÈàPÖ „ldo_vusb)vusb8-ÆÀP-ÆÀhÀ„ldo_vsram_proc2 )vsram_proc28¡ P½¶˜Lhð„ldo_vio18)vio188ð PýàhÀ„ldo_vcamio)vcamio8ð Pýàldo_vcn18)vcn188w@Pw@hðldo_vfe28)vfe288*¹€P*¹€hxldo_vcn13)vcn138 » PÖ ldo_vcn33_1_bt )vcn33_1_bt8*¹€P5gàldo_vcn33_1_wifi )vcn33_1_wifi8*¹€P5gàldo_vaux18)vaux188w@Pw@hð„ldo_vsram_others )vsram_others8¡ P½¶˜ˆhðldo_vefuse)vefuse8ð P„€ldo_vxo22)vxo228w@P!‘À„ldo_vrfck)vrfck8ã`Pð ldo_vrfck_1)vrfck8ëÀPjldo_vbif28)vbif288*¹€P*¹€hðldo_vio28)vio288*¹€P2Z „ldo_vemc)vemc8,@ P2Z ldo_vemc_1)vemc8&% P2Z JEldo_vcn33_2_bt )vcn33_2_bt8*¹€P5gàldo_vcn33_2_wifi )vcn33_2_wifi8*¹€P5gàldo_va12)va128O€PÖ „ldo_va09)va098 5PO€ldo_vrf18)vrf188ð PžPldo_vsram_md )vsram_md8¡ P½¶˜*hðldo_vufs)vufs8ð PýàJFldo_vm18)vm188ð Pýà„ldo_vbbck)vbbck8ÈàPO€ldo_vsram_proc1 )vsram_proc18¡ P½¶˜Lhð„ldo_vsim2)vsim28ð P/M`ldo_vsram_others_sshub)vsram_others_sshub8¡ P½¶rtcmediatek,mt6358-rtcspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi yp� #pmifspmimstÅ"8Õ"¬µ##"8(¼pmif_sys_ckpmif_tmr_ckspmimst_clk_muxiommu@10315000mediatek,mt8188-iommu-infray1P(ìJPmailbox@10320000mediatek,mt8188-gcey2@(âùµ#J\mailbox@10330000mediatek,mt8188-gcey3@(äùµ#J^scp@10720000mediatek,mt8188-scp-dualyr#cfg+¯PEokayscp@0mediatek,scp-corey #sram(ÎEokay4J_scp@d0000mediatek,scp-corey ð#sram(Ï Edisabledaudio-controller@10b10000mediatek,mt8188-afey±Å"SÕ"„´µ5! ! "³"´"µ"¶"¸"S"" "E"Q"M"N"O"P2"„"†"·"T"Rÿ¼clk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iec(66 !7 (audiosysÈ#4" EdisabledJadsp@10b80000mediatek,mt8188-dsp@y¸ и°¸ð#cfgsramsecbusÅ"Dµ"D"E¼audiodspadsp_busF89Mrxtx6  Edisabledmailbox@10b861004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxy¸a(ÞùJ8mailbox@10b871004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxy¸q(ßùJ9clock-controller@10b91100mediatek,mt8188-adsp-audio26my¹×J2serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uarty(� µ5# ¼baudbusEokayXdefaultf:serial@11001200*mediatek,mt8188-uartmediatek,mt6577-uarty(Ž µ5# ¼baudbus Edisabledserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uarty(� µ5# ¼baudbus Edisabledserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uarty(Ó µ5# ¼baudbus Edisabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadcy µ#¼mainEokaysyscon@11003000"mediatek,mt8188-pericfg-aosyscony0×J1spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+y (¿µ"y"#¼parent-clksel-clkspi-clkEokayXdefaultf;thermal-sensor@1100b000mediatek,mt8188-lvts-apy° (ȵ#!#p<|lvts-calib-data-1�Jpwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwmyàµ"'#/¼mainmm(Ë£ Edisabledpwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwmyðµ"(#F¼mainmm(£ Edisabledspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+y(Àµ"y"#2¼parent-clksel-clkspi-clkEokayXdefaultf=spi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+y (Áµ"y"#3¼parent-clksel-clkspi-clkEokayXdefaultf>spi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+y0(µ"y"#4¼parent-clksel-clkspi-clk Edisabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+y€(õ"y"#8¼parent-clksel-clkspi-clk Edisabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+y�(ĵ"y"#9¼parent-clksel-clkspi-clk Edisabledusb@11201000#mediatek,mt8188-mtu3mediatek,mtu3 y -ÿ > #macippc¯ ?+(€Å")Õ"vµ1 "Å1 ¼sys_ckref_ckmcu_ck®?@³ ÁAh Edisabledusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciy#mac(�Å"*Õ"vµ1 ¼sys_ckEokayethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10ay@(ÌØmacirq0µ11"A"B"C1 .¼axiapbmac_mainptp_refrmii_internalmac_cgÅ"A"B"CÕ" "¢"£6è#ùB CD/:E Edisabledmdiosnps,dwmac-mdio+stmmac-axi-configR\lJBrx-queues-config|’JCqueue0£¶queue1£¶queue2£¶queue3£¶tx-queues-configÎäJDqueue0£öqueue1£öqueue2£öqueue3£ömmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc y#õ(ƒ µ"###M!¼sourcehclksource_cgcrypto_clkEokayH) ëÂ7IXgt…�“¡E­FXdefaultstate_uhsfGºHmmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc y$ë(‡µ"##$¼sourcehclksource_cgÅ"Õ"� Edisabledmmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc y%æ(ˆµ"##A¼sourcehclksource_cgÅ"Õ"� Edisabledthermal-sensor@11278000mediatek,mt8188-lvts-mcuy'€(ʵ#!#p<|lvts-calib-data-1�Ji2c@11280000mediatek,mt8188-i2c y("€€(—ĵI#7 ¼maindma+EokayXdefaultfJ‹€i2c@11281000mediatek,mt8188-i2c y("€€(’ĵI#7 ¼maindma+EokayXdefaultfK‹€i2c@11282000mediatek,mt8188-i2c y( "€€(“ĵI#7 ¼maindma+EokayXdefaultfL‹€clock-controller@11283000mediatek,mt8188-imp-iic-wrap-cy(0×JIusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 y*-ÿ*> #macippc¯*?+(Å"-Õ"vµ1"Ë1¼sys_ckref_ckmcu_ck®M³ ÁAp Edisabledusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciy#mac(Å".Õ"vµ1¼sys_ckEokayusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 y+-ÿ+> #macippc¯+?+(Å",Õ"vµ1"É1¼sys_ckref_ckmcu_ck®N³ ÁA` Edisabledusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciy#mac(Å"+Õ"vµ1¼sys_ckEokaypcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pciey/  #pcie-mac¯‚ ÎÿmpciØ+0µ#L###&#+#C1 /¼pl_250mtl_26mtl_96mtl_32kperi_26mperi_memÐ(`éOOOO÷ Pÿÿ ®Q #pcie-phy6!7(mac Edisabledinterrupt-controllerÐøJOspi@1132c000(mediatek,mt8188-normediatek,mt8186-nory2Àµ"X11 ¼spisfaxiÅ"X(9+EokayXdefaultfRflash@0jedec,spi-nory -ut-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3¯Â+6 Edisabledpcie-phy@0yµ"ļref ?JQdsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txyȵ5 ämipi_tx0_pll× ? EdisabledJsdsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txyɵ5 ämipi_tx0_pll× ? EdisabledJti2c@11e00000mediatek,mt8188-i2c yà"€(˜ÄµS#7 ¼maindma+EokayXdefaultfT‹€i2c@11e01000mediatek,mt8188-i2c yà"€€(”ĵS#7 ¼maindma+EokayXdefaultfU‹€clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-wyà ×JSt-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+¯ãEokayusb-phy@0yµ"Ê! ¼refda_ref ?JNt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+¯äEokayusb-phy@0yµ"Æ! ¼refda_ref ?J?usb-phy@700y µ!5 ¼refda_ref ?J@t-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+¯èEokayusb-phy@0yµ"Ì! ¼refda_ref ?JMi2c@11ec0000mediatek,mt8188-i2c yì"€€(•ĵV#7 ¼maindma+EokayXdefaultfW‹€i2c@11ec1000mediatek,mt8188-i2c yì"€(–ĵV#7 ¼maindma+EokayXdefaultfX‹€clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-enyì ×JVefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuseyò+dp-calib@1a0y  Jzlvts1-calib@1acy¬@J<gpu-speedbin@581y� JJZsocinfo-data1@7a0y socinfo-data2@7e0yàgpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jmy@µY0(~} ØjobmmugpupZ |speed-bin O[666 ccore0core1core2; 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Ò`Jesyscon@14f00000mediatek,mt8188-vppsys1sysconyð×J&mutex@14f01000mediatek,mt8188-vpp-mutexyð({µ&&6 ˆ^ smi@14f02000mediatek,mt8188-smi-larbyð µ&&¼apbsmi6 Á ÒhJwsmi@14f03000mediatek,mt8188-smi-larbyð0µ&&¼apbsmi6 Á Ò`Jdclock-controller@15000000mediatek,mt8188-imgsysy×clock-controller@15110000 mediatek,mt8188-imgsys1-dip-topy×clock-controller@15130000mediatek,mt8188-imgsys1-dip-nry×clock-controller@15220000mediatek,mt8188-imgsys-wpe1y"×clock-controller@15330000mediatek,mt8188-ipesysy3×clock-controller@15520000mediatek,mt8188-imgsys-wpe2yR×clock-controller@15620000mediatek,mt8188-imgsys-wpe3yb×clock-controller@16000000mediatek,mt8188-camsysy×J)clock-controller@1604f000mediatek,mt8188-camsys-rawayð×J,clock-controller@1606f000mediatek,mt8188-camsys-yuvayð×J-clock-controller@1608f000mediatek,mt8188-camsys-rawbyð×J*clock-controller@160af000mediatek,mt8188-camsys-yuvby ð×J+clock-controller@17200000mediatek,mt8188-ccusysy ×video-decoder@18000000mediatek,mt8188-vcodec-dec y@¯` �]æ+ ´_video-codec@10000mediatek,mtk-vcodec-latyÅ"4Õ"x µ"4''"x¼selvdeclattop(ÄH �]à]á]â]ã]ä]å]æ]ç]è6video-codec@25000mediatek,mtk-vcodec-coreyPÅ"4Õ"x µ"4(("x¼selvdeclattop(ÃX �gÀgÁgÂgÃgÄgÅgÆgÇgÈgÉgÊ6smi@1800d000mediatek,mt8188-smi-larbyе''¼apbsmi6 Á Ò`Jfclock-controller@1800f000mediatek,mt8188-vdecsys-socyð×J'smi@1802e000mediatek,mt8188-smi-larbyàµ((¼apbsmi6 Á ÒhJyclock-controller@1802f000mediatek,mt8188-vdecsysyð×J(clock-controller@1a000000mediatek,mt8188-vencsysy×J/smi@1a010000mediatek,mt8188-smi-larbyµ//¼apbsmi6 Á ÒhJxvideo-encoder@1a020000mediatek,mt8188-vcodec-ency+Å"3Õ"pµ/ ¼venc_sel(aX �g g¡g¢g£g¤g¶g·g¸g¹gªgº6 ´_jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgencyµ/¼jpgenc(b �g§g¨g©g¬6jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdecyµ//¼jpgdec-smijpgdec(c0 �g­g®g²g³g´gµ6ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovlyµ%(| �g6 ˆ\ports+port@0yendpointport@1yendpoint îiJjrdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdmay µ%(~ �] 6 ˆ\ ports+port@0yendpoint îjJiport@1yendpoint îkJlcolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-colory0µ%(6 ˆ\0ports+port@0yendpoint îlJkport@1yendpoint îmJnccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorry@µ%(€6 ˆ\@ports+port@0yendpoint înJmport@1yendpoint îoJpaal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalyPµ% (�6 ˆ\Pports+port@0yendpoint îpJoport@1yendpoint îqJrgamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gammay`µ%(‚6 ˆ\`ports+port@0yendpoint îrJqport@1yendpointdither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherypµ%(ƒ6 ˆ\pports+port@0yendpointport@1yendpointdsi@1c008000mediatek,mt8188-dsiy€µ%%s¼enginedigitalhs(„®s #dphy6!% Edisableddsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dscy�µ% (…6 ˆ\�dsi@1c012000mediatek,mt8188-dsiy µ% %t¼enginedigitalhs(Ž®t #dphy6!%  Edisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergey@µ% .¼mergemerge_async(�6 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Edisabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrpy@Pp� °À4#mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dshµ.0.+...,./.-.<.1.2.3.4.5"ƒ¼mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top(6 �]d]e6(!.1.2.3.4.5p ˆ\@\P\p\�\ \°\Àpadding@1c11d000mediatek,mt8188-disp-paddingyе.6 ˆ\Ðpadding@1c11e000mediatek,mt8188-disp-paddingyàµ. 6 ˆ\àpadding@1c11f000mediatek,mt8188-disp-paddingyðµ.!6 ˆ\ðpadding@1c120000mediatek,mt8188-disp-paddingyµ."6 ˆ\padding@1c121000mediatek,mt8188-disp-paddingyµ.#6 ˆ\padding@1c122000mediatek,mt8188-disp-paddingy µ.$6 ˆ\ padding@1c123000mediatek,mt8188-disp-paddingy0µ.%6 ˆ\0padding@1c124000mediatek,mt8188-disp-paddingy@µ.&6 ˆ\@edp-tx@1c500000mediatek,mt8188-edp-txyP€(¤pz|dp_calibration_data6 )¤ Edisableddp-tx@1c600000mediatek,mt8188-dp-txy`€(Êpz|dp_calibration_data6 ) Edisabledchosen :serial0:115200n8memory@40000000mmemoryy@€reserved-memory+¯memory@50000000shared-dma-poolyP� FJ4 compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upinput-enabledrive-strengthbias-pull-downbias-disable#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namespinctrl-namespinctrl-0nvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphyswakeup-sourcemediatek,syscon-wakeupinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthhs400-ds-delaymax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplypinctrl-1clock-divbus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-namesspi-max-frequency#phy-cellsbitsoperating-points-v2power-domain-names#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzstdout-pathno-map