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Qd g utripsgpu-alert L  passive"gpu-crit 8   criticalcooling-mapsmap0  npu-thermal Q g utripsnpu-crit 8   criticaltsadc@fec00000rockchip,rk3588-tsadc5(tsadcapb_pclk<LuVWotsadc-apbtsadc    defaultsleep Bokay"adc@fec10000rockchip,rk3588-saradc 5(saradcapb_pclkuU osaradc-apbBokay +"i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c5 (i2cpclkCdefault+Bokayusb-typec@22 fcs,fusb302" default 7Bokayconnectorusb-c-connector CUSB-C Idual SB@ edual pd z, sourceports+port@0endpoint8"%port@1endpoint8"port@2endpoint8"rtc@51haoyu,hym8563Qhym8563default  i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c5 (i2cpclkDdefault+ Bdisabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c5 (i2cpclkEdefault+ Bdisabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ5(spiclkapb_pclkfm mktxrx default+ Bdisabledefuse@fecc0000rockchip,rk3588-otp 5(otpapb_pclkphyarbu ootpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[5p (apb_pclk"mphy@fed60000rockchip,rk3588-hdptx-phy 5T(refapb{8u#cde!""ophyapbinitcmnlaneroplllcpll Bdisabledphy@fed80000rockchip,rk3588-usbdp-phy{5lV(refclkimmortalpclkutmi(u   oinitcmnlanepcs_apbpma_apb    Bokay    "$port+endpoint@08"endpoint@18"phy@fee00000rockchip,rk3588-naneng-combphy5vW (refapbpipe<L{u<Cophyapb -+ ?Bokay"rphy@fee20000rockchip,rk3588-naneng-combphy5xW (refapbpipe<L{u>Eophyapb -+ ?Bokay"*sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl+"gpio@fd8a0000rockchip,gpio-bank5qr  U  $"gpio@fec20000rockchip,gpio-bank5st  U  $"gpio@fec30000rockchip,gpio-bank5uv  U@  $gpio@fec40000rockchip,gpio-bank5wx  U`  $"sgpio@fec50000rockchip,gpio-bank5yz  U  $"pcfg-pull-up a"pcfg-pull-down n"pcfg-pull-none }"pcfg-pull-none-drv-level-2 } "pcfg-pull-up-drv-level-1 a "pcfg-pull-up-drv-level-2 a "pcfg-pull-none-smt } "auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout "emmc-bus8 "emmc-clk "emmc-cmd "emmc-data-strobe "eth1fspifspim0-pins` "~gmac1gmac1-miim "ygmac1-rx-bus20  "{gmac1-tx-bus20    "zgmac1-rgmii-clk "|gmac1-rgmii-bus@ "}gpuhdmii2c0i2c0m2-xfer ",i2c1i2c1m0-xfer  "i2c2i2c2m0-xfer   "i2c3i2c3m0-xfer   "i2c4i2c4m0-xfer   "i2c5i2c5m0-xfer   "i2c6i2c6m3-xfer   "i2c7i2c7m0-xfer   "i2c8i2c8m0-xfer   "i2s0i2s0-lrck "i2s0-sclk "i2s0-sdi0 "i2s0-sdi1 "i2s0-sdi2 "i2s0-sdi3 "i2s0-sdo0 "i2s0-sdo1 "i2s0-sdo2 "i2s0-sdo3 "i2s1i2s1m0-lrck "i2s1m0-sclk "i2s1m0-sdi0 "i2s1m0-sdi1 "i2s1m0-sdi2 "i2s1m0-sdi3 "i2s1m0-sdo0  "i2s1m0-sdo1  "i2s1m0-sdo2  "i2s1m0-sdo3  "i2s2i2s2m1-lrck "i2s2m1-sclk  "i2s2m1-sdi  "i2s2m1-sdo  "i2s3i2s3-lrck "i2s3-sclk "i2s3-sdi "i2s3-sdo "jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp "pmupwm0pwm0m0-pins "0pwm1pwm1m0-pins "1pwm2pwm2m0-pins "2pwm3pwm3m0-pins "3pwm4pwm4m0-pins  "pwm5pwm5m0-pins "pwm6pwm6m0-pins  "pwm7pwm7m0-pins  "pwm8pwm8m0-pins  "pwm9pwm9m0-pins  "pwm10pwm10m0-pins  "pwm11pwm11m0-pins  "pwm12pwm12m0-pins  "pwm13pwm13m0-pins  "pwm14pwm14m0-pins  "pwm15pwm15m0-pins  "refclksatasata0sata1sata2sdiosdiom1-pins` "sdmmcsdmmc-bus4@ "sdmmc-clk "sdmmc-cmd "sdmmc-det "spdif0spdif1spi0spi0m0-pins0 "spi0m0-cs0 "spi0m0-cs1 "spi1spi1m1-pins0 "spi1m1-cs0 "spi1m1-cs1 "spi2spi2m2-pins0  "spi2m2-cs0 "spi3spi3m1-pins0  "spi3m1-cs0 "spi3m1-cs1 "spi4spi4m0-pins0 "spi4m0-cs0 "spi4m0-cs1 "tsadctsadc-shut-org "uart0uart0m1-xfer  "/uart1uart1m1-xfer   "uart2uart2m0-xfer  "uart3uart3m1-xfer   "uart4uart4m1-xfer   "uart5uart5m1-xfer   "uart6uart6m1-xfer   "uart7uart7m1-xfer   "uart8uart8m1-xfer   "uart9uart9m1-xfer   "vopbt656gpio-functsadc-gpio-func "leds-gpio "hym8563hym8563-int "usb-typecusbc0-int "typec5v-pwren "opp-table-cluster0operating-points-v2 " opp-1008000000 < L L~ @opp-1200000000 G 4 4~ @opp-1416000000 Tfr ~ @ opp-1608000000 _" P P~ @opp-1800000000 kI ~~~ @opp-table-cluster1operating-points-v2 "opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-table-cluster2operating-points-v2 "opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-tableoperating-points-v2"!opp-300000000  L L Popp-400000000 ׄ L L Popp-500000000 e L L Popp-600000000 #F L L Popp-700000000 )' ` ` Popp-800000000 / q q Popp-900000000 5 5 5 Popp-1000000000 ; P P Pchosen serial2:1500000n8adc-keys adc-keys  buttons "w@ <dbutton-recovery CRecovery Jh Uleds gpio-ledsdefaultled-1  Cstatus_led oheartbeatvbus-typec-regulatorregulator-fixed  sdefault vbus_typecLK@LK@B-"vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@"-vcc-3v3-sd-s0-regulatorregulator-fixed  vcc_3v3_sd_s02Z2ZB"vcc3v3-pcie20-regulatorregulator-fixed  vcc3v3_pcie20w@w@ PB-"t compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesno-mapclock-namespower-domainsstatusmali-supplydr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkusb-role-switchremote-endpointsnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerreset-gpiosvpcie3v3-supplyrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayreset-assert-usreset-deassert-ussnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-sd-highspeeddisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyrockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-cssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyvbus-supplylabeldata-roleop-sink-microwattpower-rolesink-pdossource-pdostry-power-rolewakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfmode-switchorientation-switchsbu1-dc-gpiossbu2-dc-gpiosrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallinux,codepress-threshold-microvoltlinux,default-triggerenable-active-highgpiostartup-delay-us