Ð þízT8s (4rèradxa,e20crockchip,rk3528 + 7Radxa E20Caliases=/pinctrl/gpio@ff610000C/pinctrl/gpio@ffaf0000I/pinctrl/gpio@ffb00000O/pinctrl/gpio@ffb10000U/pinctrl/gpio@ffb20000[/soc/ethernet@ffbe0000e/soc/i2c@ffa58000j/soc/mmc@ffbf0000o/soc/mmc@ffc30000t/soc/serial@ff9f0000cpus+cpu-mapcluster0core0|core1|core2|core3|cpu@0arm,cortex-a53€„cpu�psciž¥¹Äcpu@1arm,cortex-a53€„cpu�psciž¥¹Äcpu@2arm,cortex-a53€„cpu�psciž¥¹Äcpu@3arm,cortex-a53€„cpu�psciž¥¹Äfirmwarescmi arm,scmi-smcÌ‚× +protocol@14€ÝÄopp-table-cpuoperating-points-v2êÄopp-1200000000õG†Œ ü Yø YøÈà œ@opp-1416000000õTfr üHHÈà œ@opp-1608000000õ_Ø" üà˜à˜Èà œ@opp-1800000000õkIÒ üÔ¼Ô¼Èà œ@opp-2016000000õx)¸ üÈàÈàÈà œ@opp-table-gpuoperating-points-v2Ä1opp-300000000õᣠü Yø YøB@opp-500000000õÍe ü Yø YøB@opp-600000000õ#ÃF ü Yø YøB@opp-700000000õ)¹' ü »  » B@opp-800000000õ/¯ ü~ð~ðB@pinctrlrockchip,rk3528-pinctrl' +4Ä gpio@ff610000rockchip,gpio-bank€ÿaž r s ;GFVb nƒÄagpio@ffaf0000rockchip,gpio-bank€ÿ¯ž ‘ ’ ;IFVb nƒ” Ägpio@ffb00000rockchip,gpio-bank€ÿ°ž $ % ;KFVb @ nƒ” gpio@ffb10000rockchip,gpio-bank€ÿ±ž › œ ;LFVb ` nƒ” gpio@ffb20000rockchip,gpio-bank€ÿ²ž ä å ;NFVb € nƒ” ÄNpcfg-pull-up¢Äpcfg-pull-none¯Äpcfg-pull-none-drv-level-0¯¼Äpcfg-pull-none-drv-level-2¯¼Äpcfg-pull-up-drv-level-2¢¼Äpcfg-pull-none-smt¯ËÄarmclkemmcemmc-bus8€àÄOemmc-clkàÄPemmc-cmdàÄQemmc-strbàÄRethfephyfephym0-led-linkàÄAfephym0-led-spdàÄBfspigpuhdmihsmi2c0i2c1i2c1m0-xfer àÄ5i2c2i2c2m1-xfer àÄ6i2c3i2c4i2c4-xfer àÄ7i2c5i2c6i2c7i2c7-xfer àÄ8i2s0i2s1jtagpciepciem1-pins0àÄpdmpmupwm0pwm1pwm1m0-pinsàÄ9pwm2pwm2m0-pinsàÄ:pwm3pwm4pwm5pwm6pwm7pwrrefrgmiirgmii-miim àÄHrgmii-rx-bus20àÄJrgmii-tx-bus20àÄIrgmii-rgmii-clk àÄKrgmii-rgmii-bus@à ÄLscrsdio0sdio0-bus4@àÄSsdio0-clkàÄTsdio0-cmdàÄUsdio1sdio1-bus4@à ÄVsdio1-clkàÄWsdio1-cmdàÄXsdmmcsdmmc-bus4@àÄYsdmmc-clkàÄZsdmmc-cmdàÄ[sdmmc-detàÄ\sdmmc-vol-ctrl-hàÄfspdifspi0spi1tsi0tsi1uart0uart0m0-xfer àÄ4uart1uart2uart3uart4uart5uart6uart7ethernetgmac1-rstn-làÄMgpio-keysuser-keyàÄ`ledslan-led-gà Äbsys-led-gàÄcwan-led-gàÄdpsciarm,psci-1.0arm,psci-0.2—smcreserved-memory+4shmem@10f000arm,scmi-shmem€ðîÄ timerarm,armv8-timer0;   clock-xin24m fixed-clockõn6xin24mÝÄclock-gmac50m fixed-clockõúð€gmac0ÝÄsoc simple-bus4üüD+pcie@fe000000*rockchip,rk3528-pcierockchip,rk3568-pcie0€þ@þOüdbiapbconfig"ÿ(ž ° ± ² ® ¯$,aclk_mstaclk_slvaclk_dbipclkaux„pciH;œ�š›™ž8syspmcmsglegacyerrmsiƒH`[iz‰“ ˜pcie-phy” T4üüü ü à@¢ d b ©pwrpipe+µokay¼defaultÊ Ôàlegacy-interrupt-controllern  ;›ƒÄinterrupt-controller@fed01000 arm,gic-400@€þÐþÐ þÐ@ þÐ`  ; nƒÄqos@ff200000rockchip,rk3528-qossyscon€ÿ qos@ff200080rockchip,rk3528-qossyscon€ÿ € qos@ff200100rockchip,rk3528-qossyscon€ÿ  qos@ff200200rockchip,rk3528-qossyscon€ÿ  qos@ff200280rockchip,rk3528-qossyscon€ÿ € qos@ff200300rockchip,rk3528-qossyscon€ÿ  qos@ff200380rockchip,rk3528-qossyscon€ÿ € qos@ff210000rockchip,rk3528-qossyscon€ÿ! qos@ff210080rockchip,rk3528-qossyscon€ÿ!€ qos@ff220000rockchip,rk3528-qossyscon€ÿ" Äqos@ff220080rockchip,rk3528-qossyscon€ÿ"€ Äqos@ff240000rockchip,rk3528-qossyscon€ÿ$ qos@ff250000rockchip,rk3528-qossyscon€ÿ% Äqos@ff260000rockchip,rk3528-qossyscon€ÿ& Äqos@ff270000rockchip,rk3528-qossyscon€ÿ' Äqos@ff270080rockchip,rk3528-qossyscon€ÿ'€ Ä qos@ff270100rockchip,rk3528-qossyscon€ÿ' Ä!qos@ff270200rockchip,rk3528-qossyscon€ÿ' Ä"qos@ff270280rockchip,rk3528-qossyscon€ÿ'€ Ä#qos@ff270300rockchip,rk3528-qossyscon€ÿ' Ä$qos@ff270380rockchip,rk3528-qossyscon€ÿ'€ Ä%qos@ff270480rockchip,rk3528-qossyscon€ÿ'€ Ä&qos@ff270500rockchip,rk3528-qossyscon€ÿ' Ä'qos@ff280000rockchip,rk3528-qossyscon€ÿ( Ä(qos@ff280080rockchip,rk3528-qossyscon€ÿ(€ Ä)qos@ff280100rockchip,rk3528-qossyscon€ÿ( Ä*qos@ff280180rockchip,rk3528-qossyscon€ÿ(€ Ä+qos@ff280200rockchip,rk3528-qossyscon€ÿ( Ä,qos@ff280280rockchip,rk3528-qossyscon€ÿ(€ Ä-qos@ff280300rockchip,rk3528-qossyscon€ÿ( Ä.qos@ff280380rockchip,rk3528-qossyscon€ÿ(€ Ä/qos@ff280400rockchip,rk3528-qossyscon€ÿ( Ä0syscon@ff340000rockchip,rk3528-vpu-grfsyscon€ÿ4€ÄCsyscon@ff348000$rockchip,rk3528-pipe-phy-grfsyscon€ÿ4€€Ä^syscon@ff360000rockchip,rk3528-vo-grfsyscon€ÿ6Ä=clock-controller@ff4a0000rockchip,rk3528-cru€ÿJ˜ð t          z y  LL€FÏq;šÊ;]ÁQ–æ²€Íeúð€õáðÑ€ ëÂá£Cýׄ#ÃFúð€õásY@Íež ,xin24mgmac0ÝÄ syscon@ff540000rockchip,rk3528-ioc-grfsyscon€ÿTÄ power-management@ff600000&rockchip,rk3528-pmusysconsimple-mfd€ÿ` power-controller!rockchip,rk3528-power-controller"+Ä power-domain@4€ž Ð Ë6"power-domain@5€6" µdisabledpower-domain@6€6"power-domain@7€$6 !"#$%&'"power-domain@8€$6()*+,-./0"gpu@ff700000"rockchip,rk3528-maliarm,mali-450€ÿpð гÜ@ᣞ Ð ,buscoreT;XYV\]Z["8gpgpmmupppp0ppmmu0pp1ppmmu1¥1” ¢ wµokay=2spi@ff9c0000(rockchip,rk3528-spirockchip,rk3066-spi€ÿœž â á,spiclkapb_pclk ;ƒI33Ntxrx” + µdisabledspi@ff9d0000(rockchip,rk3528-spirockchip,rk3066-spi€ÿ�ž ž �,spiclkapb_pclk ;„I33Ntxrx” + µdisabledserial@ff9f0000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿŸž  k,baudclkapb_pclk ;(I3 3Xeµokay¼defaultÊ4serial@ff9f8000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿŸ€ž  ë,baudclkapb_pclk ;)I3 3 ” Xe µdisabledserial@ffa00000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ ž   ,baudclkapb_pclk ;*I3 3 ” Xe µdisabledserial@ffa08000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ €ž  ì,baudclkapb_pclk ;+I33” Xe µdisabledserial@ffa10000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¡ž  1,baudclkapb_pclk ;,I33” Xe µdisabledserial@ffa18000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¡€ž " ¡,baudclkapb_pclk ;-I33” Xe µdisabledserial@ffa20000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¢ž % ¢,baudclkapb_pclk ;.I33” Xe µdisabledserial@ffa28000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¢€ž ( £,baudclkapb_pclk ;/I33” Xe µdisabledi2c@ffa50000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¥ž ß Þ ,i2cpclk ;=” + µdisabledi2c@ffa58000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¥€ž Ý Ü ,i2cpclk ;>” +µokay¼defaultÊ5eeprom@50belling,bl24c16aatmel,24c16€Pox‚i2c@ffa60000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¦ž j i ,i2cpclk ;?¼defaultÊ6+ µdisabledi2c@ffa68000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¦€ž ¥ ¤ ,i2cpclk ;@” + µdisabledi2c@ffa70000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ§ž 3 2 ,i2cpclk ;A¼defaultÊ7” + µdisabledi2c@ffa78000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ§€ž § ¦ ,i2cpclk ;B” + µdisabledi2c@ffa80000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¨ž © ¨ ,i2cpclk ;C” + µdisabledi2c@ffa88000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¨€ž 5 4 ,i2cpclk ;D¼defaultÊ8” + µdisabledpwm@ffa90000(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©ž o n ,pwmpclk� µdisabledpwm@ffa90010(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©ž o n ,pwmpclk�µokay¼defaultÊ9Ägpwm@ffa90020(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ© ž o n ,pwmpclk�µokay¼defaultÊ:Ähpwm@ffa90030(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©0ž o n ,pwmpclk� µdisabledpwm@ffa98000(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©€ž r q ,pwmpclk� µdisabledpwm@ffa98010(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©€ž r q ,pwmpclk� µdisabledpwm@ffa98020(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©€ ž r q ,pwmpclk� µdisabledpwm@ffa98030(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©€0ž r q ,pwmpclk� µdisabledadc@ffae0000rockchip,rk3528-saradc€ÿ®ž à Â,saradcapb_pclk ;Œ” ¢ o ©saradc-apb˜µokayª;Ä_ethernet@ffbd0000&rockchip,rk3528-gmacsnps,dwmac-4.20a€ÿ½0ž      >,stmmacethclk_mac_refmac_clk_rxmac_clk_txpclk_macaclk_mac;qt8macirqeth_wake_irq¶<Ármii” ¢ ´ ©stmmaceth'=Ê>Úë?þ@ µdisabledmdiosnps,dwmac-mdio+ethernet-phy@2ethernet-phy-ieee802.3-c22€ž "¼defaultÊAB¢ ¸Ä<stmmac-axi-config,6FÄ>rx-queues-configVÄ?queue0tx-queues-configlÄ@queue0ethernet@ffbe0000&rockchip,rk3528-gmacsnps,dwmac-4.20a€ÿ¾ ž ­ ¬ « ª(,stmmacethclk_mac_refpclk_macaclk_mac;y|8macirqeth_wake_irq” ¢ a ©stmmaceth'CÊDÚëEþFµokay‚output¶G Árgmii-id�¼defaultÊHIJKLmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22€¼defaultÊMšN ª†  ÔNÄGstmmac-axi-config,6FÄDrx-queues-configVÄEqueue0tx-queues-configlÄFqueue0mmc@ffbf00000rockchip,rk3528-dwcmshcrockchip,rk3588-dwcmshc€ÿ¿ð � � Œ  ëÂn6 ëÂ(ž Œ � Ž � �,corebusaxiblocktimer ;ˆ¼ ë¼defaultÊOPQR” (¢ A B C D E©corebusaxiblocktimerµokayÊÔæõû;mmc@ffc100000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc€ÿÁ@ ž ¹ ¸ — ˜,biuciuciu-driveciu-sample* ;‰¼ ë¼default ÊSTU” ¢ g©reset µdisabledmmc@ffc200000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc€ÿÂ@ ž » º ™ š,biuciuciu-driveciu-sample* ;м ë¼default ÊVWX” ¢ h©reset µdisabledmmc@ffc300000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc€ÿÃ@ ž ( ' • –,biuciuciu-driveciu-sample* ;…¼ðÑ€¼defaultÊYZ[\” ¢ ½©reset5ZµokayÊÔSdo]dma-controller@ffd60000arm,pl330arm,primecell€ÿÖ@ž ^ ,apb_pclkl;}ˆÄ3phy@ffdc0000rockchip,rk3528-naneng-combphy€ÿÜð {õáž { ³ ´ ,refapbpipe” ¢ c e©phyapbŸªC¼^µokayÄchosenÒserial0:1500000n8adc-keys adc-keysÞ_êbuttonsûw@dbutton-maskrom#MASKROM)�4gpio-keys gpio-keys¼defaultÊ`button-user Úa#USER)Nleds gpio-leds¼default Êbcdled-lan\boffplan ÚN ynetdevled-sys\bon pheartbeat ÚN yheartbeatled-wan\boffpwan ÚNynetdevregulator-0v9-vddregulator-fixed�vdd_0v9ž²Ä » Ü » ôeregulator-1v1-vcc-ddrregulator-fixed�vcc_ddrž²ÄÈàÜÈàôeregulator-1v8-vccregulator-fixed�vcc_1v8ž²Äw@Üw@ôÄ;regulator-3v3-vccregulator-fixed�vcc_3v3ž²Ä2Z Ü2Z ôeÄregulator-5v0-vcc-sysregulator-fixed �vcc5v0_sysž²ÄLK@ÜLK@Äeregulator-vccio-sdregulator-gpio ÚN¼defaultÊf �vccio_sdÄw@Ü2Z ÿw@2Z ôeÄ]regulator-vdd-armpwm-regulatorgˆ e�vdd_armž²Ä bÜShúÄregulator-vdd-logicpwm-regulatorhˆ e �vdd_logicž²Ä ÁèÜY°úÄ2 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4ethernet0i2c1mmc0mmc1serial0cpuregdevice_typeenable-methodclocksoperating-points-v2cpu-supplyphandlearm,smc-idshmem#clock-cellsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrangesinterruptsgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspower-domainsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsno-mapclock-frequencyclock-output-namesreg-namesbus-rangeclock-namesinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-lanesphysphy-namesresetsreset-namesstatuspinctrl-namespinctrl-0reset-gpiosvpcie3v3-supplyassigned-clocksassigned-clock-rates#reset-cells#power-domain-cellspm_qosmali-supplydmasdma-namesreg-io-widthreg-shiftpagesizeread-onlyvcc-supply#pwm-cells#io-channel-cellsvref-supplyphy-handlephy-modesnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-is-integratedsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useclock_in_outphy-supplyreset-assert-usreset-deassert-usmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vno-sdno-sdionon-removablevmmc-supplyvqmmc-supplyfifo-depthrockchip,default-sample-phasecap-sd-highspeeddisable-wpsd-uhs-sdr104#dma-cellsarm,pl330-periph-burst#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltwakeup-sourcecolordefault-statefunctionlinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplystatespwmspwm-supplyregulator-settling-time-up-us